Don’t send a generic resume — generate a resume and cover letter tailored to this exact role.
Cadence is seeking a Senior Engineer for the System Verification Group to advance Xcelium, the industry-leading RTL/logic simulator, addressing the scale of future AI and hyperscale chip designs.
You will refine algorithms for SDC constraints, improve compilation speed, and lead a distributed team of engineers in delivering high-quality RTL/logic simulation features.
Join the team behind Xcelium, the industry-leading logic simulator, to architect the next generation of hardware verification technology. As a Senior Engineer in the System Verification Group, you will be at the forefront of EDA innovation, evolving the Xcelium simulator to meet the staggering complexity of future AI and hyperscale chip designs. You will be part of an innovative, geographically distributed team dedicated to advancing the capabilities of RTL/logic simulation for semiconductor technology. The work environment encourages collaboration, technical excellence, and continuous learning.
We are looking for experienced C++ software engineers who thrive on "impossible" scaling challenges and want to invent the algorithms that will power tomorrow’s silicon.
Responsibilities:
Position Requirements/Qualifications:
The annual salary range for California is $210,000 to $390,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.