Senior Software Architect

RiseMe

San Jose (CA)

On-site

USD 210,000 - 390,000

Full time

2 days ago
Be an early applicant
Application generator

Don’t send a generic resume — generate a resume and cover letter tailored to this exact role.

Get past ATS filters

Benefits offered by this job

PTO & Holidays
401(k) with match
Stock purchase plan
Medical/Dental/Vision

Job summary

Cadence is seeking a Senior Engineer for the System Verification Group to advance Xcelium, the industry-leading RTL/logic simulator, addressing the scale of future AI and hyperscale chip designs.

You will refine algorithms for SDC constraints, improve compilation speed, and lead a distributed team of engineers in delivering high-quality RTL/logic simulation features.

Qualifications

  • MS in Computer Science or Electrical Engineering with extensive experience (12+ years) or PhD with 10+ years of experience.
  • 10+ years of EDA software development experience.

Responsibilities

  • Enhance and support Xcelium RTL/logic simulator engine with new features.
  • Tune Timing Constraints Verification technology used inside Xcelium.
  • Design and optimize graph algorithms for multi-billion-node graphs with SDC constraints.
  • Perform deep-dive bottleneck analyses; optimize C/C++ for speed and memory.
  • Lead junior engineers; collaborate across a distributed team.

Skills

C++/C
RTL/Logic Simulation
SDC constraints
Timing Analysis
Multithreading
Learning new tech

Education

MS in CS or EE
PhD (preferred)

Tools

SystemVerilog

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Join the team behind Xcelium, the industry-leading logic simulator, to architect the next generation of hardware verification technology. As a Senior Engineer in the System Verification Group, you will be at the forefront of EDA innovation, evolving the Xcelium simulator to meet the staggering complexity of future AI and hyperscale chip designs. You will be part of an innovative, geographically distributed team dedicated to advancing the capabilities of RTL/logic simulation for semiconductor technology. The work environment encourages collaboration, technical excellence, and continuous learning.

We are looking for experienced C++ software engineers who thrive on "impossible" scaling challenges and want to invent the algorithms that will power tomorrow’s silicon.

Responsibilities:

  • Enhance and support Xcelium RTL/logic simulator engine to add new features and extend existing features.
  • Enhance and support Timing Constraints Verification technology used inside Xcelium simulator.
  • The role involves designing, tuning, and innovating graph algorithms involving SDC constraints support on multi‑billion‑node graphs.
  • Conduct deep-dive bottleneck analysis and implement performance optimizationsin C/C++ to improve compilation speed and memory footprint.
  • Lead junior engineers and collaborate with global team members to deliver high-quality results in a distributed environment.
  • Contribute to technical discussions, code reviews, and process improvements.
  • Write Specifications and Unit Tests for your code.

Position Requirements/Qualifications:

  • MS in Computer Science or Electrical Engineering with a minimum of 12 years of experience OR PhD with a minimum of 10 years of experience
  • 10+ years of experience in EDA software development.
  • Strong background in RTL/Logic Simulation, SDC constraints and Timing Analysis especially path exceptions handling in a STA tool.
  • Excellent programming skills in C/C++ and a deep understanding of SystemVerilogor Verilog.
  • Experience in multi-threaded/ concurrent programming.
  • Ability to quickly learn new technologies and adapt to project requirements.
  • Prior experience with RTL/logic simulation software development is an added plus.

The annual salary range for California is $210,000 to $390,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.
Get your free, confidential resume review.

or drag and drop your file here.

Similar jobs

Similar jobs worth comparing

Senior Principal Software Engineer
Senior Principal Software Engineer

RiseMe • San Jose (CA)

On-site
USD 161,000 - 299,000
Bonus
Equity
Benefits package
+2
Senior Principal Software Engineer
Senior Principal Software Engineer

Cadence Design Systems • San Jose (CA)

On-site
USD 161,000 - 299,000
Senior Software Architect
Senior Software Architect

Cadence Design Systems • San Jose (CA)

On-site
USD 210,000 - 390,000
Paid vacation and paid holidays
401(k) with employer match
Employee stock purchase plan
Sr. Principal Software Engineer, Physical Verification
Sr. Principal Software Engineer, Physical Verification

Cadence • San Jose (CA)

On-site
USD 161,000 - 299,000
Software Architect, Physical Verification
Software Architect, Physical Verification

Cadence • San Jose (CA)

On-site
USD 178,000 - 332,000
Paid Vacation
401(k) plan with employer match
Employee Stock Purchase Plan
+1
Lead Software Engineer
Lead Software Engineer

Cadence Design Systems • New Jersey

On-site
USD 102,000 - 189,000
Senior RTL/Logic Simulation Architect
Senior RTL/Logic Simulation Architect

Cadence Design Systems • San Jose (CA)

On-site
USD 210,000 - 390,000
Paid vacation and paid holidays
401(k) with employer match
Employee stock purchase plan
Principal Design Engineer
Principal Design Engineer

Cadence • San Jose (CA)

On-site
USD 136,000 - 254,000
Paid vacation and holidays
401(k) plan with employer match
Employee stock purchase plan
+1
Principal Design Engineer
Principal Design Engineer

Cadence • Cary (NC)

On-site
USD 136,000 - 254,000
401(k) plan with employer match
Employee stock purchase plan
Medical, dental, and vision plans
Software Engineer (new college grad Dec 2026)
Software Engineer (new college grad Dec 2026)

Cadence Design Systems • San Jose (CA)

On-site
USD 102,000 - 189,000
Paid vacation
401(k) matching
Employee stock purchase
+2