Senior SOC Verification Engineer for AI Accelerated Chips

Amazon Inc.; Austin (TX); On-site; USD 185,000 - 250,000; Full time

Benefits offered by this job

Health insurance

RSUs

401(k) matching

Paid time off

Job summary

Amazon Web Services seeks an experienced Design Verification Engineer to design and optimize custom silicon in data centers. You will verify SOC designs, integrate IPs, and develop robust test benches, testplans, and coverage strategies.

The role emphasizes mentoring junior engineers and maintaining regression infrastructure. Qualifications include a Bachelor's degree or higher in CS/CE/EE and 8+ years in design verification using SystemVerilog/UVM, with 8+ years in testbench development.

Qualifications

• Bachelor's degree or above in Computer Science, Computer Engineering, Electrical Engineering, or related fields.
• 8+ years of design verification experience using SystemVerilog and UVM.
• 8+ YOE in testbench development including: stimulus, checkers, assertions and coverage.

Responsibilities

• Verify custom chip designs at the SOC level.
• Integrate 3rd party IPs and VIPs into the SOC testbench.
• Create comprehensive testplans, write robust random testcases, and execute coverage plans.
• Maintain autosmoke and regression infrastructure.
• Dive deep into bugs and triages.
• Mentor junior engineers.

Skills

SystemVerilog

UVM

C/C++

Python

AMBA protocols

PCIe/UCIe

Memory subsystems

CPU/GPU/ML accelerators

Education

Bachelor's degree or above in CS/CE/EE

Tools

Verification platforms

Job description

Amazon Web Services seeks an experienced Design Verification Engineer to design and optimize custom silicon in data centers. You will verify SOC designs, integrate IPs, and develop robust test benches, testplans, and coverage strategies.

The role emphasizes mentoring junior engineers and maintaining regression infrastructure. Qualifications include a Bachelor's degree or higher in CS/CE/EE and 8+ years in design verification using SystemVerilog/UVM, with 8+ years in testbench development.