Lead SoC Verification Architect

Annapurna Labs; Cupertino (CA); On-site; USD 277,000 - 350,000; Full time

Job summary

Amazon Web Services (AWS) Custom Silicon within Annapurna Labs in Cupertino, CA seeks a Principal Design Verification Engineer to own verification of high-speed I/O and SoC subsystems. You will drive end-to-end verification strategies, develop robust testbenches, and lead cross‑functional collaboration with design, architecture, and software teams.

The role requires 8+ years in design verification, expert UVM/constrained-random experience, and proficiency across FV, emulation, and

Qualifications

• Bachelor's degree in Electrical Engineering or related field.
• 8+ years of design verification experience using constrained-random simulation techniques (such as UVM).
• 8+ years of experience in testbench development including stimulus, checkers, assertions and coverage.

Responsibilities

• Architect and implement end-to-end verification strategies addressing system-wide implications and cross-module interactions
• Drive unified verification plans across multiple environments, tools and methodologies
• Provide technical leadership for verification efforts, guiding architectural decisions and methodology choices
• Own the technical direction and drive resolution of complex verification challenges at sub-system and chip-level, providing hands-on technical guidance and effective solutions
• Guide and mentor team members on best practices, methodology improvements, and technical problem-solving

Skills

Constrained-random verification

Testbench development

UVM

Education

Bachelor's degree in Electrical Engineering

Tools

Python

Perl

C/C++

Java

C#

Job description

Amazon Web Services (AWS) Custom Silicon within Annapurna Labs in Cupertino, CA seeks a Principal Design Verification Engineer to own verification of high-speed I/O and SoC subsystems. You will drive end-to-end verification strategies, develop robust testbenches, and lead cross‑functional collaboration with design, architecture, and software teams.

The role requires 8+ years in design verification, expert UVM/constrained-random experience, and proficiency across FV, emulation, and