Senior SoC Verification Architect

Renesas Electronics Corporation; Austin (TX); On-site; USD 120,000 - 190,000; Full time

Benefits offered by this job

Competitive benefits package

Job summary

Renesas Electronics Corporation is seeking a Senior Digital Design Verification Engineer to lead verification of complex power-management SoCs across architecture, RTL design, firmware, and validation teams.

You will build reusable UVM environments, develop test plans, and drive coverage closure through regression data. Strong SystemVerilog fluency and scripting are essential for success in this role.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field.
• 4 or more years of relevant digital design verification experience, or equivalent directly applicable experience.
• Demonstrated ownership of a complex block, subsystem, or major feature from verification planning through closure.
• Strong proficiency in SystemVerilog, UVM, constrained random verification, functional coverage, and SystemVerilog Assertions.

Responsibilities

• Own verification of complex digital blocks or major SoC features from requirements analysis through coverage closure.
• Develop feature-based verification plans from product, architecture, and microarchitecture specifications; identify gaps, ambiguities, corner cases, and risks.
• Build and extend reusable SystemVerilog/UVM environments, including sequences, monitors, scoreboards, checkers, assertions, and coverage models.
• Develop constrained random and targeted tests for normal operation, error handling, recovery, and system-level interactions.
• Drive functional, code, toggle, FSM, and assertion coverage closure using regression and coverage data.
• Debug RTL, testbench, assertion, integration, and regression failures; collaborate with design and firmware teams to isolate issues and verify fixes.
• Automate regression, triage, reporting, and analysis workflows using scripting and modern engineering tools.
• Communicate status, risks, dependencies, and closure evidence clearly; provide technical guidance to less-experienced engineers.

Skills

SystemVerilog

UVM

Constrained random

Coverage driven verification

Debug

Regression analysis

Linux scripting (Python)

Education

Bachelor's or Master’s degree in Electrical Engineering or related field

Tools

Cadence Xcelium

SimVision

vManager

JasperGold

Synopsys VCS

Verdi

Job description

Renesas Electronics Corporation is seeking a Senior Digital Design Verification Engineer to lead verification of complex power-management SoCs across architecture, RTL design, firmware, and validation teams.

You will build reusable UVM environments, develop test plans, and drive coverage closure through regression data. Strong SystemVerilog fluency and scripting are essential for success in this role.