Senior SoC Digital Verification Architect

Renesas Electronics Corp.; Austin (TX); On-site; USD 120,000 - 180,000; Full time

Job summary

Renesas Electronics Corp. is seeking a Senior Digital Design Verification Engineer in Austin to lead verification of complex power-management SoCs. You will own planning, release closure, and collaborate with architecture, RTL, firmware, and validation teams to ensure robust digital blocks and features.

You will develop feature-based verification plans, build reusable SystemVerilog/UVM environments, and drive constrained random tests and coverage closure in a cross-disciplinary team environment.

Qualifications

• Experience with SystemVerilog/UVM based verification environments.
• Proven ability to translate specs into test plans and coverage criteria.
• Own verification planning and closure for complex blocks or SOC features.
• Strong debugging of RTL, testbench, and regression failures.

Responsibilities

• Own verification of complex digital blocks or major SoC features from requirements through coverage closure.
• Develop feature-based verification plans from product and architecture specs.
• Build reusable SystemVerilog/UVM environments with sequences, monitors, scoreboards, and assertions.
• Create constrained random and targeted tests for normal and fault conditions.
• Drive coverage closure using regression and coverage data; triage failures.
• Debug RTL, testbench, and regression issues; collaborate with design and firmware teams.
• Automate regression, triage, reporting, and analysis workflows.
• Communicate status, risks, and closure evidence clearly to stakeholders.

Skills

SystemVerilog

UVM

Constrained random verification

Functional coverage

SystemVerilog Assertions

Debugging

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Tools

Cadence Xcelium

SimVision

vManager

JasperGold

Synopsys VCS

Verdi

Job description

Renesas Electronics Corp. is seeking a Senior Digital Design Verification Engineer in Austin to lead verification of complex power-management SoCs. You will own planning, release closure, and collaborate with architecture, RTL, firmware, and validation teams to ensure robust digital blocks and features.

You will develop feature-based verification plans, build reusable SystemVerilog/UVM environments, and drive constrained random tests and coverage closure in a cross-disciplinary team environment.