SoC Timing (Static Timing Analysis/STA) Engineer, HBM

micron; Richardson (TX); On-site; USD 150,000 - 210,000; Full time

Benefits offered by this job

Medical, dental and vision plans

Job summary

Micron is seeking an experienced Static Timing Analysis (STA) Engineer in Texas to own chip-level timing sign-off for next‑generation die. You will collaborate with RTL, physical design, DFT, verification, and product teams to ensure timing integrity from design through tape-out.

The role focuses on constraint authoring, timing closure, and automation, with mentorship of engineers and involvement in build documentation and timing assets.

Qualifications

• 10+ years of hands-on chip-level STA ownership.
• Expertise with PrimeTime/Tempus for timing sign-off.
• Strong knowledge of MMMC, OCV, POCV concepts.

Responsibilities

• Own end-to-end chip-level STA sign-off across modes and temps.
• Develop and maintain SDC constraints for clocks, resets, and HBM interfaces.
• Drive timing closure with RTL, PnD, DFT, and product teams.
• Lead timing correlation and sign-off governance.

Skills

Timing analysis

Python scripting

Tcl scripting

Tools

Synopsys PrimeTime

Cadence Tempus

Job description

Our vision is to transform how the world uses information to enrich life for all .

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

The Heterogeneous Integration Group (HIG) within Micron's Technology and Products Group (TPG) leads the development of High Bandwidth Memory (HBM) solutions for AI and ML applications. Our modern designs use Through Silicon Via (TSV) technology. We stack multiple DRAM chips on a high-speed memory controller with a coordinated logic chip in one package. This new way improves memory density and bandwidth through parallelization. It aims to deliver the lowest power per bit solutions in the industry.

As a Static Timing Analysis (STA) Engineer - you will be part of the Heterogeneous Integration Group (HIG), owning chip-level timing sign-off for next-generation die. You will work closely with RTL design, physical design, architecture, DFT, verification, and product teams to ensure timing integrity and drive timing closure across all modes and corners from initial design through tape-out.

This is a hands-on senior technical role focused on chip-level STA ownership, constraint authoring, timing closure, methodology development, and pre-/post-silicon timing correlation.

Key Responsibilities

Responsibilities will include, but are not limited to:

• Own end-to-end chip-level static timing analysis and sign-off across all checks, modes, corners, and voltage and temperature conditions.
• Develop, maintain, and validate sign-off quality Synopsys Design Constraints (SDC) for clocks, resets, high-bandwidth memory (HBM) interfaces, design for test (DFT), and configuration logic.
• Drive timing closure at block, subsystem, and full-chip levels through critical path analysis, engineering change orders (ECOs), and close collaboration with physical design on placement, clock tree synthesis, and routing.
• Perform multi-mode, multi-corner (MMMC) analysis including clock domain crossing timing, on-chip variation (OCV, AOCV, POCV), and advanced-node timing methodologies.
• Lead signal integrity and crosstalk analysis, identify noise-induced timing issues, and partner with physical design teams on mitigation strategies.
• Build and maintain static timing analysis automation and flows using Python and Tcl for reporting, regression tracking, quality of results dashboards, and sign-off readiness.
• Conduct post-silicon timing correlation. Define and drive organization-wide static timing analysis methods, sign-off standards, timing closure guidelines, readiness reviews, and tape-out sign-off gates. Clearly communicate timing status, risks, and closure plans to build leads and senior management.
• Mentor and support engineers early in their careers. Contribute to build documentation and timing sign-off artifacts. Collaborate with Physical Build, RTL Build, Verification, Build for Test, Product Engineering, and Test teams to ensure timing requirements are met throughout the build cycle.

Minimum Qualifications

• 10+ years of hands-on experience owning chip-level static timing analysis and full timing sign-off on multiple tape-outs at 5nm or below.
• Deep expertise with industry-standard static timing analysis tools such as Synopsys PrimeTime and/or Cadence Tempus.
• Expert understanding of advanced timing concepts including multi-mode multi-corner analysis, on-chip variation, signal integrity, and power-aware timing.
• Proven ability to develop and manage complex hierarchical SDC constraints for large systems on chip with multiple clock and power domains.
• Proficiency in Python and/or Tcl scripting for timing flow automation, constraint management, and quality of results reporting.

Preferred Qualifications

• Experience with high-bandwidth memory (HBM), dynamic random-access memory (DRAM), or memory-centric system-on-chip designs.
• Exposure to design for test timing, including scan, memory built-in self-test (MBIST), and Joint Test Action Group (JTAG) interfaces.
• Experience with chiplet-based or three-dimensional integrated circuit designs and die-to-die interface timing methodologies.
• Familiarity with foundry process design kits, Liberty timing models, and advanced noise and variation modeling.
• Strong communication skills with the ability to present timing status, risks, and sign-off readiness to multi-functional teams and senior leadership.
• Good understanding of Agentic AI or willingness to learn Agentic AI to help develop efficient workflow.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth.

Benefits

• Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future.
• We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget.