Senior SoC Power Modeling Lead (Pre-Silicon)

Advanced Micro Devices, Inc.; Austin (TX); Hybrid; USD 140,000 - 200,000; Full time

Job summary

AMD is seeking a Sr. engineer in Austin, TX to own end‑to‑end SoC power modeling for CPU/GPU/NPU, fabric, memory, and I/O. You will define use‑case power envelopes, drive DVFS/AVFS strategies, and deliver FPY/telemetry requirements for FW hand‑offs.

Strong experience with PowerArtist, PrimeTime PX, and Python automation is essential. You will collaborate with Architecture, RTL/Design, Physical Design, FW/BIOS, and System PnP to ensure converged Perf/Watt outcomes from concept through bring‑up,

Qualifications

• Experience in pre-silicon power modeling and estimation.
• Strong collaboration across Architecture, RTL/Design, Physical Design, FW/BIOS, and System PnP.

Responsibilities

• Own the SoC power model end-to-end for CPU/GPU/NPU, fabric, memory and I/O.
• Define use-case power envelopes across automotive, networking, storage, industrial and robotics segments.
• Drive DVFS/AVFS strategy, telemetry requirements, and FW hand-offs based on model outputs.
• Establish IP/subsystem power budgets and guide architectural decisions.
• Build model-to-silicon correlation plans and maintain a power scorecard.

Skills

SoC power modeling

EDA/tooling

DVFS/AVFS

x86 micro-architecture knowledge

Power-related FW telemetry

Python automation

Power model correlation

Education

B.S./M.S. in EE/CE/CS

Tools

PowerArtist

PrimeTime PX

FSDB/VCD

UPF/CPF

Job description

AMD is seeking a Sr. engineer in Austin, TX to own end‑to‑end SoC power modeling for CPU/GPU/NPU, fabric, memory, and I/O. You will define use‑case power envelopes, drive DVFS/AVFS strategies, and deliver FPY/telemetry requirements for FW hand‑offs.

Strong experience with PowerArtist, PrimeTime PX, and Python automation is essential. You will collaborate with Architecture, RTL/Design, Physical Design, FW/BIOS, and System PnP to ensure converged Perf/Watt outcomes from concept through bring‑up,