Senior SoC Micro-Architect & RTL Designer for AI Silicon

Acceler8 Talent; Mountain View (CA); Hybrid; USD 180,000 - 220,000; Full time

Job summary

Acceler8 Talent in Mountain View, CA, is seeking an experienced ASIC/SoC engineer for a hybrid role (on-site Tuesday–Thursday). The team is building a new processor architecture tailored for frontier-scale language models, with a base salary of $200k+ plus RSUs.

You will translate architectural requirements into production-quality RTL, own blocks from spec through sign-off, and develop high-performance compute, memory, or interconnect functionality while optimizing timing, power and area.

Qualifications

• 5+ years of SoC/ASIC microarchitecture and RTL design experience.
• Strong SystemVerilog skills, plus Python or C/C++ experience.
• Experience taking complex designs toward production silicon.
• Hands-on knowledge of synthesis, lint, CDC, and equivalence checking.
• Experience delivering high-performance compute, memory, or connectivity designs.
• Understanding RTL decisions impact on timing, power, area, and physical implementation.

Responsibilities

• Translate architectural requirements into production-quality microarchitecture and RTL.
• Own blocks or subsystems from specification through sign-off.
• Develop compute, memory-management, or high-speed-connectivity functionality.
• Optimize performance, power, area, and timing.
• Work across verification, DFT, physical design, architecture, and software.
• Support silicon bring-up and debug.

Skills

RTL design

SystemVerilog

Python/C++

Production silicon

Synthesis

Lint

CDC

Timing/PPA

High-performance compute

Job description

Acceler8 Talent in Mountain View, CA, is seeking an experienced ASIC/SoC engineer for a hybrid role (on-site Tuesday–Thursday). The team is building a new processor architecture tailored for frontier-scale language models, with a base salary of $200k+ plus RSUs.

You will translate architectural requirements into production-quality RTL, own blocks from spec through sign-off, and develop high-performance compute, memory, or interconnect functionality while optimizing timing, power and area.