Senior SoC Digital Design Engineer – Video Codec

TikTok Inc.; San Jose (CA); On-site; USD 218,000 - 480,000; Full time

Benefits offered by this job

Medical, dental, and vision insurance

401(k) with company match

Paid parental leave

Short-term and long-term disability

Life insurance

Wellbeing benefits

10 paid holidays per year

10 paid sick days per year

17 days Paid Personal Time

Job summary

TikTok Inc. in San Jose, CA is seeking a video codec hardware design engineer to build scalable accelerators for encoding/processing. You will design RTL, define SoC architecture, and collaborate across verification, backend, and power teams.

The role emphasizes Verilog/SystemVerilog mastery, front-end design experience, and proficiency with EDA tools, plus scripting for automation. Join a fast-growing hardware team shaping next-generation codecs.

Qualifications

• Bachelor's degree or higher in Microelectronics, ICs, CS, Electrical Engineering, or related field.
• 3+ years of experience in digital front-end design.
• Mastery of Verilog/SystemVerilog and a solid foundation in digital circuits.
• Proficiency with mainstream front-end EDA tools (e.g., Spyglass, Design Compiler, PrimeTime).
• Fluent in at least one scripting language (Python, Perl, Tcl, Makefile) for workflow automation.

Responsibilities

• Define the architecture of SoC top/subsystems and evaluate PPA in early design.
• Write RTL code (Verilog/SystemVerilog) and maintain design documentation.
• Perform Lint, CDC, and RDC checks to ensure code quality.
• Collaborate with Verification, Backend and Mid-end teams on Synthesis, SDC, STA and power optimization.
• Contribute to chip low-power strategies using Clock Gating and Power Gating; support UPF flow.

Skills

Verilog/SystemVerilog

Front-end design

Scripting languages

Education

Bachelor's degree or higher in Microelectronics, ICs, CS, EE, or related field

Master's degree in a related field

Tools

Spyglass

Design Compiler

PrimeTime

Job description

TikTok Inc. in San Jose, CA is seeking a video codec hardware design engineer to build scalable accelerators for encoding/processing. You will design RTL, define SoC architecture, and collaborate across verification, backend, and power teams.

The role emphasizes Verilog/SystemVerilog mastery, front-end design experience, and proficiency with EDA tools, plus scripting for automation. Join a fast-growing hardware team shaping next-generation codecs.