Senior SoC/ASIC Physical Design Engineer
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Xcelerium is a fabless semiconductor company developing advanced edge processors that bring AI processing to high-bandwidth sensors and wireless devices, unlocking hidden insights from every RF signal.
Working at Xcelerium offers the opportunity to work on complex development projects from the ground up and to become familiar with cutting-edge technologies such as wireless signal processing, computer vision, sensor fusion, machine learning, and frameworks like TensorFlow, PyTorch, OpenCL, and OpenGL. The application domains include 5G, UAVs/Drones, Robots, and Autonomous Vehicles, providing vast scope for growth and impact.
About the Job
As a Senior SoC/ASIC Physical Design Engineer, you will develop and implement flows and methodologies for physical implementation to optimize performance, power efficiency, and area.
Responsibilities
- Perform partition synthesis and physical implementation steps (e.g., synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency, and other signoff checks)
- Develop and improve physical design methodologies and automation scripts for various implementation steps
- Collaborate closely with the ASIC design team to drive architectural feasibility studies, develop timing, power, and area targets, and explore RTL/design tradeoffs
- Resolve design/timing/congestion and flow issues, identify solutions, and drive execution
- Run, debug, and fix signoff closure issues in static timing analysis (STA), noise, logic equivalency, physical verification, electromigration, and voltage drop
Qualifications
- Bachelor’s degree in electrical engineering, computer engineering, or computer science
- 10+ years of ASIC and/or physical design flow development experience
- Experience with ASIC physical design, flows, and methodologies (synthesis, place and route, STA, formal verification, CDC, power analysis) using industry-standard tools
- Scripting experience with Python, Tcl, or Perl
- Experience in extraction of design parameters, QOR metrics, trend analysis, voltage scaling (SVS, DVFS), and SRAM split rail implementation
- Strong experience in ASIC/SOC RTL2GDSII physical design and signoff flows
- Proficiency with Synopsys EDA tools and understanding of their capabilities and algorithms
- Deep knowledge of deep sub-micron FinFET and CMOS physics
- Understanding of CMOS digital design principles, standard cells, and libraries
- Knowledge of CMOS power dissipation, leakage, and dynamic power
- Familiarity with CMOS analog circuit and physical design
- Knowledge of DFT/Scan/MBIST/LBIST and their impact on physical design flows
- Self-driven with a positive attitude, eager to learn, and able to work in a dynamic team environment
We offer a competitive compensation package.
Seniority level
Employment type
Job function
- Engineering and Information Technology
Industries
- Software Development, Technology, Information and Media, Telecommunications
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