Staff ASIC Design Engineer

HRB; United States; Remote; USD 120,000 - 180,000; Full time

Job summary

Join a forward-thinking company as a Staff ASIC Design Engineer, where you'll play a key role in developing cutting-edge IP for ASICs and FPGAs. This position requires a blend of creativity and analytical skills to tackle complex design challenges. You will leverage your extensive experience in ASIC design and methodologies, ensuring that designs meet industry best practices. Collaborate with a talented team in an Agile environment, contributing to innovative solutions and leading technical initiatives. If you're passionate about driving advancements in hardware design, this role is an exciting opportunity to make a significant impact.

Qualifications

• 10+ years of experience in ASIC design with successful tape outs.
• Strong knowledge in RTL programming languages and design methodologies.

Responsibilities

• Design and oversee hardware architectures for ASIC development.
• Simulate, test, and verify hardware designs using Verilog/SystemVerilog.

Skills

ASIC Design

Verilog/SystemVerilog

TCL/Python

Agile Development

Problem Solving

Education

B.S in Electrical Engineering

M.S in Electrical Engineering

Ph.D in Electrical Engineering

Tools

Physical Design Tools

Power Estimation Design Tools

Job description

We are looking for aStaff ASIC Design Engineerto contribute to a team developing IP for both ASICs and FPGAs. The ideal candidate is a strong communicator, creative, a critical thinker, and able to analyze and resolve complex issues.

Responsibilities

• • Apply industry best practices in ASIC development to achieve best in class designs
  • Design, propose, and oversee the analysis/evaluation of hardware architectures
  • Design and code RTL modules written in Verilog/SystemVerilog
  • Simulate and perform hardware-based testing, debug, and verification
  • Scripting and basic software development in support of hardware design
  • Apply Agile development methodologies including code reviews, sprint planning, and frequent deployment

Requirements

• • B.S, M.S, or Ph.D in Electrical Engineering, Computer Engineering or Computer Science
  • Track record of successful tape outs in advanced process nodes
  • 10+ years of experience in ASIC design
  • Experience in ASIC design methodologies, including code quality checking, synthesis, physical design, and power estimation design tools
  • Strong knowledge with RTL programming languages Verilog/SystemVerilog (preferred), or VHDL
  • Ability to read and write code in TCL/Python (C, C++ are assets)

Preferred Skills & Experience

• • Deep experience with ASIC or FPGA timing closure and physical design
  • Working experience with AMBA protocols, PCIe, UCIe, and HBM will be an asset
  • Experience with Agile development methodologies
  • Experience in technical leadership of small teams