Senior SoC Architect: Lead High-Speed I/O & System Design

Ayar Labs, Inc.; San Jose (CA); Vor Ort; USD 250.000 - 304.000; Vollzeit

Zusammenfassung

Ayar Labs, Inc. is seeking a Senior Principal Engineer – SoC Architect to define and drive next-generation SoC architectures for high-performance semiconductor products.

You will lead architecture across compute, memory, interconnects, and security with emphasis on high-speed interfaces and power/performance optimization. You will mentor engineers, coordinate across hardware, firmware, software, and verification teams, and guide architectural methodologies through multiple product generations.

Qualifikationen

• Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field.
• 15+ years of experience in SoC/system architecture and semiconductor product development.
• Proven expertise in large-scale SoC architecture definition and subsystem integration.
• Strong understanding of High-speed I/O architectures and protocols, On-chip interconnects and coherency fabrics, Memory subsystem architecture, Performance modeling and analysis and Power/performance optimization techniques.
• Experience with architecture modeling tools, simulation environments, and performance analysis methodologies.
• Strong technical communication and leadership skills.

Aufgaben

• Define end-to-end SoC architecture for complex semiconductor platforms across compute, memory, interconnect, security, and peripheral subsystems.
• Drive architectural tradeoff analysis involving performance, power, area (PPA), latency, scalability, and cost.
• Develop architectural specifications, subsystem partitioning, and top-level integration strategies.
• Collaborate with product, software, firmware, RTL, verification, physical design, and validation teams throughout the development lifecycle.
• Lead architecture and integration of high-speed interfaces including PCIe, Ethernet, USB, SerDes, CXL/UCIe and other advanced interconnect protocols.
• Define bandwidth, latency, coherency fabrics, buffering, QoS, and interoperability requirements.
• Drive system-level performance modeling and interface optimization.
• Partner with PHY, signal integrity, packaging, and board teams to ensure robust end-to-end solutions.
• Develop architectural models, traffic analysis, and workload characterization frameworks.
• Drive power-aware architecture decisions and dynamic performance management strategies.
• Provide architectural leadership across multiple SoC programs and product generations.
• Mentor senior engineers and influence organization-wide architectural methodologies.
• Lead technical reviews, design evaluations, and architecture signoff discussions.
• Drive alignment across hardware, firmware, software, and platform ecosystems.

Kenntnisse

SoC architecture

Leadership

High-speed I/O

Performance modeling

Cross-functional leadership

Power optimization

Ausbildung

Bachelor's/Master's/PhD in EE/CE

Tools

PCIe Gen5/Gen6

CXL/UCIe

HBM

SerDes

Jobbeschreibung

Ayar Labs, Inc. is seeking a Senior Principal Engineer – SoC Architect to define and drive next-generation SoC architectures for high-performance semiconductor products.

You will lead architecture across compute, memory, interconnects, and security with emphasis on high-speed interfaces and power/performance optimization. You will mentor engineers, coordinate across hardware, firmware, software, and verification teams, and guide architectural methodologies through multiple product generations.