Senior SoC Architect: Lead High-Performance Interconnects

Ayar Labs; San Jose (CA); On-site; USD 250,000 - 304,000; Full time

Job summary

Ayar Labs is seeking a highly experienced Senior Principal Engineer to define and drive next-generation SoC architectures in San Jose, CA. This pivotal role requires deep expertise in system-level architecture and high-speed I/O integration.

The successful candidate will lead architectural decisions, collaborate with cross-functional teams, and influence long-term SoC technologies. The role offers a competitive salary range between $250,000 and $304,000.

Qualifications

• 15+ years of experience in SoC/system architecture and semiconductor product development.
• Proven expertise in large-scale SoC architecture definition.
• Strong understanding of high-speed I/O architectures and protocols.

Responsibilities

• Define end-to-end SoC architecture for complex semiconductor platforms.
• Drive architectural tradeoff analysis involving performance, power, area, latency.
• Collaborate with various teams throughout the development lifecycle.

Skills

System-level architecture

High-speed I/O integration

Performance optimization

Cross-functional technical leadership

Architectural innovation

Education

Bachelor’s, Master’s, or PhD in Electrical Engineering or related field

Tools

Architecture modeling tools

Simulation environments

Job description

Ayar Labs is seeking a highly experienced Senior Principal Engineer to define and drive next-generation SoC architectures in San Jose, CA. This pivotal role requires deep expertise in system-level architecture and high-speed I/O integration.

The successful candidate will lead architectural decisions, collaborate with cross-functional teams, and influence long-term SoC technologies. The role offers a competitive salary range between $250,000 and $304,000.