Senior SoC Timing Analysis Engineer — Hybrid Role

Intel; Phoenix (AZ); Hybrid; USD 164,000 - 269,000; Full time

Job summary

Intel is seeking an experienced Senior Static Timing Analysis (STA) Engineer to drive development of next-generation SoC products. You will partner with architecture, logic design, clocking, DFT and physical design teams to ensure timing convergence, performance, and power efficiency across complex SOCs.

In this role you will develop flows, timing models, and constraints, set PVT conditions, and help optimize clock networks.

Qualifications

• Bachelor's degree in Computer Engineering, CS, or related STEM with 6+ years of experience.
• Master's degree in related STEM with 4+ years of experience.
• 5+ years of SOC timing analysis, clock network design, and timing closure.

Responsibilities

• Perform SOC level timing analysis and optimization, ensuring designs meet functional and performance requirements.
• Generate and verify timing constraints while addressing timing violations at the chip or block level for SoCs.
• Conduct timing rollups and develop optimized clock networks for functionality, performance, and power efficiency.
• Define methodologies to produce high-quality timing models and enable efficient physical design execution.
• Establish the appropriate PVT conditions for timing analysis, aligning with product plans and binning strategies.
• Work closely with the clocking team and full-chip designers to balance timing fixes, power delivery, clocking, and partitioning.
• Collaborate with architecture, clocking design, DFT and logic design teams to develop flows for chip integration and validate clock network performance guidelines.
• Contribute to the development of tools, flows, and methodologies that enhance SoC physical design and timing processes.

Skills

SOC timing analysis

Clock network design

Timing closure methodologies

TCL scripting

Cross-functional collaboration

Education

Bachelor's degree in Computer Engineering or Computer Science

Master's degree in related STEM field

Tools

Timing extraction tools

Physical design tools

Clocking tools

Job description

Intel is seeking an experienced Senior Static Timing Analysis (STA) Engineer to drive development of next-generation SoC products. You will partner with architecture, logic design, clocking, DFT and physical design teams to ensure timing convergence, performance, and power efficiency across complex SOCs.

In this role you will develop flows, timing models, and constraints, set PVT conditions, and help optimize clock networks.