Senior Silicon Photonics Layout Engineer - Equity & Impact

NVIDIA Corporation; Santa Clara (CA); On-site; USD 148,000 - 236,000; Full time

Benefits offered by this job

Equity

Benefits

Job summary

NVIDIA Corporation is seeking a Senior Photonic Layout Design Engineer to own physical design and verification of photonic ICs, guiding from proof-of-concept to high‑volume manufacturing. You will collaborate across photonics, CMOS, packaging, and systems teams to advance SiPh and SERDES products.

The role requires 12+ years in layout design with Cadence Virtuoso, proficiency in programming (Python/ SKILL/ Perl/ TCL/ C++), and experience with industry verification tools.

Qualifications

• BS, MS, or Ph.D. in Electrical Engineering, Physics, or closely related field (or equivalent).
• 12+ years of hands-on, full-chip layout design in semiconductor, analog or silicon photonics.

Responsibilities

• Lead physical design and verification of photonic ICs from proof-of-concept to manufacturing readiness.
• Oversee layout of waveguides, modulators, photodetectors, and high-speed I/O with tape-out ownership.
• Develop AI-assisted design methods and layout automation to improve productivity and reduce cycle times.

Skills

Cadence Virtuoso

Python

SKILL

Perl

TCL

C++

Education

Bachelor/Master/PhD in Electrical Engineering or Physics

Tools

Calibre

Hercules

ICV

Dracula

Primeyield

Job description

NVIDIA Corporation is seeking a Senior Photonic Layout Design Engineer to own physical design and verification of photonic ICs, guiding from proof-of-concept to high‑volume manufacturing. You will collaborate across photonics, CMOS, packaging, and systems teams to advance SiPh and SERDES products.

The role requires 12+ years in layout design with Cadence Virtuoso, proficiency in programming (Python/ SKILL/ Perl/ TCL/ C++), and experience with industry verification tools.