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Acceler8 Talent is aiding an early-stage photonic computing company in Berkeley to hire a Senior Photonic Layout Engineer. The role centers on owning the photonic layout and tape-out flow, integrating PIC development with electronic IC work, and establishing a Cadence workflow for a 45 nm process.
You will implement photonic and electronic layout, manage netlisting, DRC/LVS, and ensure designs meet manufacturing requirements while collaborating with a small, technically deep founding team.
We’re working with an early-stage photonic computing company developing an integrated optical-electronic platform for AI workloads. The approach uses light to address the power, data-movement and compute-density challenges of conventional electronic accelerators.
The work spans photonic compute, electronic ICs, packaging, memory and system architecture, with a focus on turning research silicon into a commercial computing platform.
They’re hiring a Senior Photonic Layout Engineer to own the photonic layout and tape-out flow, connecting PIC development with the electronic IC work already underway.
You’ll own a foundational part of a photonic computing platform while major design and integration decisions are still open. The work connects photonic devices with electronic ICs, packaging and measured hardware performance.
You’ll work directly with a technically deep founding team and help build the workflow that turns individual designs into a complete, manufacturable system.
This is an opportunity for someone who wants to take responsibility for chip-level implementation and help move photonic computing from research silicon toward a commercial product.