Photonic Layout Engineer

Acceler8 Talent

Berkeley (CA)

On-site

USD 180,000 - 240,000

Full time

2 days ago
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Job summary

Acceler8 Talent is aiding an early-stage photonic computing company in Berkeley to hire a Senior Photonic Layout Engineer. The role centers on owning the photonic layout and tape-out flow, integrating PIC development with electronic IC work, and establishing a Cadence workflow for a 45 nm process.

You will implement photonic and electronic layout, manage netlisting, DRC/LVS, and ensure designs meet manufacturing requirements while collaborating with a small, technically deep founding team.

Qualifications

  • Direct PIC design ownership of layout implementation and sign-off.
  • Hands-on Cadence expertise in photonics and electronics design flows.
  • Experience taking commercial photonic designs toward tape-out with design sign-off accountability.
  • Practical ownership of foundry PDKs, design rules, netlisting, DRC/LVS.

Responsibilities

  • Own the photonic layout flow from design implementation and routing through verification and tape-out release.
  • Establish a Cadence Photonics workflow for the target process compatible with electronic IC design flow.
  • Implement photonic and electronic layout and routing within Cadence, resolving interfaces between domains.
  • Own netlisting, DRC/LVS and foundry/PDK integration, ensuring manufacturability.

Skills

PIC layout ownership
Cadence experience
DRC/LVS verification
Foundry PDK integration
Silicon-photonics physics
Cross-domain integration
Tape-out ownership

Tools

Cadence Photonics
PDK compatibility
Layout verification tools

Job description

We’re working with an early-stage photonic computing company developing an integrated optical-electronic platform for AI workloads. The approach uses light to address the power, data-movement and compute-density challenges of conventional electronic accelerators.

The work spans photonic compute, electronic ICs, packaging, memory and system architecture, with a focus on turning research silicon into a commercial computing platform.

They’re hiring a Senior Photonic Layout Engineer to own the photonic layout and tape-out flow, connecting PIC development with the electronic IC work already underway.

The role
  • Own the photonic layout flow from design implementation and routing through verification, sign-off and tape-out release.
  • Establish a Cadence Photonics workflow for GlobalFoundries’ 45 nm process, compatible with the electronic IC design flow.
  • Personally implement photonic and electronic layout and routing within Cadence, resolving interfaces between the two domains.
  • Own netlisting, DRC/LVS and foundry/PDK integration, ensuring designs meet manufacturing requirements.
Your experience
  • Direct PIC design experience, with substantial personal ownership of layout implementation, routing and verification.
  • Strong hands-on Cadence experience, including practical work connecting photonic and electronic design flows.
  • Experience taking commercial photonic designs toward tape-out, with clear accountability for your own implementation and sign-off work.
  • Practical ownership of foundry PDKs, design rules, netlisting and DRC/LVS.
  • A strong understanding of silicon-photonics device physics, supported by device or circuit design and simulation experience.
  • The ability to work across PIC, EIC, packaging and lab validation, understanding how layout decisions affect the integrated system.
  • Comfort with hands-on execution, broad responsibility and establishing a design flow within a small team.

You’ll own a foundational part of a photonic computing platform while major design and integration decisions are still open. The work connects photonic devices with electronic ICs, packaging and measured hardware performance.

You’ll work directly with a technically deep founding team and help build the workflow that turns individual designs into a complete, manufacturable system.

This is an opportunity for someone who wants to take responsibility for chip-level implementation and help move photonic computing from research silicon toward a commercial product.

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