SI/PI Intern: High-Speed AI Hardware

The Consensus; San Jose (CA); On-site; USD 18,000 - 30,000; Part time

Benefits offered by this job

Housing support

Daily lunch and dinner in office

Direct mentorship from industry leads

Paid internship

Job summary

Etched seeks a Signal Integrity / Power Integrity Intern to help design and validate the next generation of high-performance AI systems in our San Jose office.

You will work with package, PCB, ASIC, and system engineers to analyze high-speed interfaces, extract channel models, and improve signal quality across accelerator platforms, gaining hands-on experience with PCIe, Ethernet, and SerDes challenges.

Qualifications

• Progress toward a BS, MS, or PhD in Electrical Engineering, Computer Engineering, or a related field.
• Coursework or project experience in signal integrity, electromagnetics, RF, microwave engineering, or high-speed digital design.
• Familiarity with transmission line theory and S-parameters.
• Understanding of PCB stackups, routing, and high-speed design fundamentals.
• Strong analytical and debugging skills.
• Excellent communication and collaboration skills.

Responsibilities

• Perform signal integrity analysis for high-speed interfaces including PCIe and Ethernet.
• Extract and validate S-parameter models from package and PCB layouts; analyze loss, return loss, impedance and crosstalk.
• Build and validate 3D electromagnetic models using HFSS; develop channel models from ECAD data.
• Collaborate with PCB, package, hardware, and ASIC teams to improve SI and provide design guidelines.

Skills

Signal integrity

High-speed design

Python scripting

Electromagnetics

RF engineering

Education

BS/MS/PhD in Electrical Engineering or Computer Engineering

Tools

Ansys HFSS

SIwave

ADS

CST

Allegro / IPC2581 / ODB++

Job description

Etched seeks a Signal Integrity / Power Integrity Intern to help design and validate the next generation of high-performance AI systems in our San Jose office.

You will work with package, PCB, ASIC, and system engineers to analyze high-speed interfaces, extract channel models, and improve signal quality across accelerator platforms, gaining hands-on experience with PCIe, Ethernet, and SerDes challenges.