Senior SI/PI Engineer – AI and Compute Server Design

Jobtailor; Fremont (CA); On-site; USD 150,000 - 210,000; Full time

Job summary

Jobtailor in Fremont, CA is seeking an experienced Signal Integrity and Power Integrity engineer to lead high-speed channel design, PDN targeting, and realistic routing rules for PCIe Gen5/Gen6, CXL, NVLink, and DDR5/DDR6 memory.

You will model and simulate with HFSS, ADS, HSPICE, Sigrity; build IBIS-AMI simulations and perform lab validation using oscilloscopes and VNAs to drive corrective design changes across boards, layout, and mechanical teams.

Qualifications

• 6+ years of hands-on SI/PI experience in high-speed servers, GPUs, or related high-speed digital systems.
• Proven delivery of designs into production.
• Familiar with PCIe, CXL, DDR JEDEC and Ethernet electrical specs and compliance methodologies.

Responsibilities

• Lead SI/PI analysis for high-speed interfaces (PCIe Gen5/Gen6, CXL, NVLink, DDR5/DDR6).
• Design and validate PDN impedance, decoupling, and IR-drop strategies.
• Model, simulate, and validate channel performance using HFSS/ADS/HSPICE/Sigrity; develop IBIS-AMI and S-parameter based channels.
• Perform lab validation with oscilloscopes, VNAs, TDRs; correlate simulation to lab data and drive design changes.
• Collaborate with board, layout, and mechanical teams to embed SI/PI rules into stackups and routing.

Skills

Signal Integrity

Power Integrity

Modeling & Simulation

Lab Validation

Cross-functional Collaboration

Education

Bachelor's or Master's in Electrical Engineering

Tools

HFSS

ADS

HSPICE

Sigrity

Job description

• Signal integrity analysis. Perform pre- and post-layout SI analysis for high-speed interfaces including PCIe Gen5/Gen6, CXL, NVLink, Ethernet/SerDes, and DDR5/DDR6 memory, defining channel budgets, routing rules, and equalization strategies.
• Power integrity analysis. Design and validate power delivery networks, including PDN impedance targeting, decoupling strategy, and IR-drop analysis for high-current GPU, CPU, and VR rails.
• Modeling and simulation. Build and run models using tools such as HFSS, ADS, HSPICE, Sigrity, or equivalent; develop IBIS-AMI and S-parameter-based channel simulations.
• Lab validation and correlation. Execute measurements with high-speed oscilloscopes, VNAs, TDRs, and BER testers; correlate simulation to lab data and drive corrective design changes.
• Cross-functional design support. Partner with board designers, layout, and mechanical teams to embed SI/PI rules into stackups, routing, and connector/cable selection, and support EVT/DVT/PVT bring-up and debug.

Requirements

• Education: Bachelor's or Master's in Electrical Engineering or a related field.
• Experience: 6+ years of hands-on SI/PI experience for servers, GPU platforms, or high-speed digital systems, with proven delivery of designs into production.
• Technical expertise: Strong knowledge of high-speed channel design, PDN design and analysis, connector/cable modeling, and PCB stackup/materials; proficiency with SI/PI simulation tools (e.g., HFSS, ADS, HSPICE, Sigrity) and high-speed lab measurement equipment.
• Standards: Familiarity with PCIe, CXL, DDR JEDEC, and Ethernet electrical specifications and compliance methodologies.
• Communication: Able to translate analysis into clear, actionable design guidance and collaborate effectively across board, layout, and mechanical teams.

Core Competencies

Demonstrates expertise in Signal Integrity (SI) and Power Integrity (PI) analysis for high-speed digital systems, utilizing advanced simulation tools and lab validation techniques to ensure design accuracy and compliance with industry standards.