Signal Integrity Engineer - SR Staff (Ansys HFSS, ADS, PCIe, HyperLynx)

Confidential Company; Austin (TX); On-site; USD 120,000 - 150,000; Full time

Job summary

A leading technology firm is seeking a SR Staff Signal Integrity Engineer to work onsite in Austin, TX. The position demands expertise in high-speed Signal Integrity design, along with proficiency in tools like Ansys HFSS and Cadence Allegro. Candidates are expected to possess a BSEE and have 7+ years of relevant experience. Key responsibilities include ensuring robust design for hardware solutions and collaborating across teams to improve product quality and performance. Competitive compensation and potential for sponsorship are offered.

Qualifications

• Must have 7+ years of high-speed Signal Integrity design experience.
• Expertise in PCB Stack Up Designs and lab verification required.
• Experience with 50 Gb/s or higher signaling support for Ai Data Centers.

Responsibilities

• Define and validate Signal Integrity for Networking and Server products.
• Lead design and implementation for complex Signal Integrity projects.
• Conduct simulations for memory and high-speed interfaces.

Skills

High-speed Signal Integrity design

Ansys HFSS

Cadence Allegro

PCB modeling

Strong English communication

Education

BSEE or similar

Tools

Ansys SIwave

Keysight ADS

Sigrity

Matlab

VNA

Job description

Overview

SR STAFF Signal Integrity Engineer (Ansys HFSS, Cadence Allegro, PCB, SerDes)

Fulltime position – Must work onsite in San Jose/Santa Clara or Austin, TX

CONFIDENTIAL: Publicly traded computer HARDWARE infrastructure platform solutions company with over $5 Billion in sales whose stock price has grown over 200% in the last year because their products and services are used within Ai Data Centers.

50 Gb/s and higher Signal Integrity design within a PCB stack-up, and off the board (connectors & cables)

The Signal Integrity team is experiencing dramatic growth in the USA and has several newly created openings at different levels ranging from SR Engineer, Staff, SR Staff, Principal. In general, the Signal Integrity Engineer provides design guideline and support to system architecture design, board layout, product bring up, debug, validation, and factory builds. They will also perform testing, simulation, validation and qualification of systems and makes design adjustments as needed.

The Signal Integrity Engineer works in cross-functional teams with other designers, customers, manufacturing engineering and project leadership to ensure robust and high-quality product development.

Responsibilities

• Define and develop and validate Signal Integrity for next generation technologies for Networking, Server, and Storage products used in Hardware Platform Solutions for HPC – High Performance Computing and Ai Data Centers.
• Models high-density I/O s on PCBs, packages, connectors and probe cards with respect to parameters such as reflections, bandwidth, and crosstalk.
• Lead the design, development and implementation of technical solutions for complex Signal Integrity projects, involving multiple domains. Participate in project planning and scheduling.
• Strong knowledge in simulation tools like Hspice, Sigrity, ADS, Ansys SIwave, HFSS 3D.
• Strong knowledge of Signal Integrity and Power Integrity fundamental concepts.
• Strong experience in Package and PCB modelling is required.
• Performs Transmission line & Via modelling and carry out experiments to validate modelling outcomes and methodologies.
• Should be able to analyze and review the layout files related to Signal Integrity and Power Integrity problems.
• Should be able to provide practical solutions to PCB/Package design team based on simulation results and analysis.
• Conducting Simulation of memory interfaces for Board and Package, and High-Speed Serial IO interfaces for Board and Package.

Requirements

• Must have BSEE (or similar) and 7+ years of experience with high-speed Signal Integrity design and evaluation. This includes Signal Integrity within a PCB stack up, and off the board (board to board connectors, ribbon cables, coaxial cables). This person should serve as the SME in the planning of digital PCB Stack Up Designs, simulation, lab verification, and troubleshooting while working on 50 Gb/s or higher (in support of Ai data centers) with large stacks (15+ layers, preferably 40 layers).
• Should be Signal Integrity SME (Subject Matter Expert) and skilled using Ansys HFSS, SerDes Design, Cadence Allegro, and Sigrity, Keysight ADS (Advance Design Systems) for EDA (Electronic Design Automation), Ansys SIwave, Siemens Hyperlynx, Matlab, VNA (Vector Network Analyzer).
• Should have expertise in Signal Integrity, SIPI, SerDes, PCIe, PAM4 – PCB Board & Package – Simulation & Modeling.
• Must be willing to work onsite 4 days a week in either San Jose/Santa Clara, CA or Austin, TX.
• Sponsorship is a possibility for the right skillset.
• Must have great English communication skills and ability to work with teams located around the globe. Proven ability to articulate requirements and vision to large and diverse audience through architecture specs and give verbal presentations in technical forums.