Senior SI Architect: PCIe Gen 6+/CXL for Data Center

Qualcomm; San Diego (CA); On-site; USD 221,000 - 332,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a Senior Signal Integrity Architect to own PCIe Gen 6+ and CXL SI across data center server platforms.

Lead end-to-end channel analysis, design closure, and validation planning with cross-functional teams including platform, silicon, and packaging engineers. Responsibilities include developing SI models, managing retimers and redrivers integration, and creating automation for analysis flows.

Qualifications

• 10+ years of experience in signal integrity analysis, simulation, and validation of high-speed digital systems.
• Ownership of PCIe interface SI from architecture through system validation; PCIe Gen 6 experience preferred.
• Strong knowledge of transmission-line theory, channel analysis, insertion and return loss, crosstalk, S-parameters, jitter, equalization, link margin.

Responsibilities

• Own end-to-end SI analysis and design closure for PCIe Gen 6+ and CXL interfaces from early architecture through platform validation.
• Develop channel budgets, margin analyses, design rules, signoff criteria, and correlation plans for PCIe/CXL links.
• Own SI architecture and technical guidance for PCIe REFCLK distribution and jitter-budget analysis.

Skills

PCIe Gen 6

CXL

Signal integrity

SI modeling

S-parameters

Jitter analysis

Unix/Linux

Scripting

Lab equipment

Python/MATLAB

Education

Master's degree in Electrical Engineering

Bachelor's degree in Engineering/CS/IS

PhD (preferred)

Tools

HFSS/SIwave

Cadence Sigrity/Clarity

CST

Keysight ADS

Synopsys HSPICE

IBIS-AMI

Job description

Qualcomm Technologies, Inc. is seeking a Senior Signal Integrity Architect to own PCIe Gen 6+ and CXL SI across data center server platforms.

Lead end-to-end channel analysis, design closure, and validation planning with cross-functional teams including platform, silicon, and packaging engineers. Responsibilities include developing SI models, managing retimers and redrivers integration, and creating automation for analysis flows.