Senior Server IO Architect: PCIe/CXL & Datacenter IO

Qualcomm; Santa Clara (CA); On-site; USD 284,900 - 427,300; Full time

Job summary

Qualcomm is seeking a highly experienced Server IO specialist to architect and design end‑to‑end Server IO solutions, including PCIe, CXL, and emerging technologies for datacenter SoCs.

The role involves collaboration with chip architects, IP design, performance and verification teams to optimize high‑performance, low‑power IO subsystems and to document IO architecture requirements. You will drive architectural decisions and ensure alignment with customer technical requirements.

Qualifications

• Bachelor’s degree with 10+ years of relevant experience in IO architecture.
• Master’s degree with 9+ years of relevant experience.
• PhD with 8+ years of relevant experience.
• Over 15 years of experience architecting PCIe, CXL, or similar IO technologies.
• Strong expertise in IOMMU / SMMU architecture and micro‑architecture.
• In‑depth understanding of fully coherent and IO coherent protocol flows.
• Experience with IO hardware stacks from Transport Layer to Physical Layer.

Responsibilities

• Work with chip architects to understand architecture concepts and high‑level requirements.
• Define and document IO architecture requirements and solutions for the chip.
• Collaborate with IP design and performance teams to optimize end‑to‑end IO solutions for PPA trade‑offs.
• Evangelize and communicate IO solutions to silicon, system, and software stakeholders.
• Develop architectural solutions meeting customer technical requirements for new products.
• Coordinate with design and verification teams to ensure implementation follows specifications.

Skills

IO architecture

PCIe

CXL

ARM ISA

SMMU

GIC

TDISP/IDE/TSP IO

Education

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master’s degree in related field

PhD in related field

Job description

Qualcomm is seeking a highly experienced Server IO specialist to architect and design end‑to‑end Server IO solutions, including PCIe, CXL, and emerging technologies for datacenter SoCs.

The role involves collaboration with chip architects, IP design, performance and verification teams to optimize high‑performance, low‑power IO subsystems and to document IO architecture requirements. You will drive architectural decisions and ensure alignment with customer technical requirements.