Senior Signal Integrity Architect - PCIe Gen6+/CXL

Qualcomm; Hillsboro (OR); On-site; USD 221,000 - 332,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking a senior Signal Integrity Architect to own PCIe Gen 6+ and CXL signal integrity across Qualcomm data center server platforms.

You will lead end-to-end SI analysis, define channel budgets, and guide retimer integration to ensure robust system-level designs. Collaborating with platform, silicon, package, board, firmware, and validation teams, you will develop automation for analysis flows and contribute design guides and technical reviews.

Qualifications

• Master's degree or PhD in Electrical/Computer Engineering or related field.
• Extensive experience with high-speed SI, PCIe Gen 6+ and CXL.
• Strong knowledge of transmission-line theory, jitter, and channel analysis.

Responsibilities

• Own end-to-end SI analysis and design closure for PCIe Gen6+ and CXL interfaces.
• Develop channel budgets, margin analyses, design rules, and signoff criteria.
• Guide PCIe REFCLK distribution and jitter-budget considerations.
• Lead retimer/redriver integration, placement, and model use.
• Build full-channel models and perform frequency- and time-domain simulations.

Skills

PCIe Gen6

CXL SI

Signal Integrity

Channel Modeling

S-parameters

Jitter Analysis

REFCLK Analysis

Retimers/Redrivers

Python/Matlab/Perl

Unix/Linux

Cross-Functional Leadership

Education

Master's in EE/related

PhD in EE/CE (preferred)

Bachelor's in Engineering

Tools

HFSS/SIwave

Cadence Sigrity/Clarity

CST

Keysight ADS

Synopsys HSPICE

IBIS-AMI modeling

Job description

Qualcomm Technologies, Inc. is seeking a senior Signal Integrity Architect to own PCIe Gen 6+ and CXL signal integrity across Qualcomm data center server platforms.

You will lead end-to-end SI analysis, define channel budgets, and guide retimer integration to ensure robust system-level designs. Collaborating with platform, silicon, package, board, firmware, and validation teams, you will develop automation for analysis flows and contribute design guides and technical reviews.