AI Datacenter PCIe Subsystem Architect

Qualcomm; Santa Clara (CA); On-site; USD 164,000 - 265,000; Full time

Job summary

Qualcomm Technologies, Inc. seeks an experienced PCIe Subsystem Architect to define and deliver high-performance I/O architectures for next-generation AI products in the datacenter.

The ideal candidate will have deep expertise across PCIe, CXL, UCIe, NVMe, Ethernet and related datacenter connectivity standards, and will drive subsystem architecture from accelerator cards to full-rack deployments.

Qualifications

• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
• Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
• PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
• 3+ years of experience with high-performance designs involving PCIe, Ethernet, or other high-speed I/O interfaces.

Responsibilities

• In-depth knowledge of PCIe, Ethernet, and other high-speed I/O interfaces used in datacenter and accelerator products.
• Strong understanding of PCIe ordering models, producer-consumer ordering, ARM ordering behavior, DMA flows, and high-speed serial interface behavior.
• Strong understanding of PCIe Gen6/Gen7 requirements, including FLIT mode, PAM4 signaling implications, link training, latency, error handling, and system-level tradeoffs.
• Experience with PCIe error containment and recovery mechanisms such as AER, DPC, CRS, FLR, and reset separation.
• Experience with I/O virtualization and isolation technologies such as SR-IOV, SIOV, PF/VF isolation, and related software-visible requirements.
• Strong understanding of RAS, telemetry, reliability, and security requirements for server-class SoCs and accelerator subsystems.
• Good knowledge of scale-up and scale-out architectures, including PCIe switch fabrics, NIC connectivity, host-to-accelerator orchestration, and rack-level deployment considerations.
• Ability to work effectively in a high-caliber, international, multi-site engineering team.

Skills

PCIe

Ethernet

CXL

UCIe

NVMe

I/O interfaces

Datacenter architectures

Education

Bachelor's degree in EE/CS/related field

Master's degree in EE/CS/related field

PhD in EE/CS/related field

Job description

Qualcomm Technologies, Inc. seeks an experienced PCIe Subsystem Architect to define and deliver high-performance I/O architectures for next-generation AI products in the datacenter.

The ideal candidate will have deep expertise across PCIe, CXL, UCIe, NVMe, Ethernet and related datacenter connectivity standards, and will drive subsystem architecture from accelerator cards to full-rack deployments.