Senior Digital Design Engineer

ArcTern Ventures; San Jose (CA); On-site; USD 140,000 - 190,000; Full time

Job summary

HYPERLUME in San Jose, CA is seeking a Senior PHY RTL Design Engineer to own RTL micro-architecture and drive SerDes DSP function development, verification, and timing/power integration. This role requires deep expertise in high-speed digital design and a track record delivering robust PHY IP.

Join a cutting-edge earthtech partner and collaborate with cross-functional teams to ensure reliable silicon that meets performance targets in a rapidly evolving market.

Qualifications

• Senior PHY RTL Design Engineer with hands-on RTL micro-architecture experience.
• Development of SerDes DSP functions, verification, and timing/power integration.
• Strong background in digital design for high-speed interfaces.

Responsibilities

• Design and verify RTL for PHY blocks and SerDes components.
• Analyze timing, power, and area impact and optimize performance.
• Collaborate with verification engineers and system architects to deliver robust solutions.

Skills

RTL design

DSP

SerDes

Verification

Timing analysis

Job description

If you're looking for a new challenge in the earthtech sector, we encourage you to take a look at these postings from our thriving partner companies

HYPERLUME

Software Engineering, Design

San Jose, CA, USA

Posted on Aug 28, 2026

About the role Senior PHY RTL Design Engineer responsible for RTL micro-architecture and development of SerDes DSP functions, verification, and timing/power integration.