Senior SerDes Bring-Up Validation Engineer

Astera Labs; San Jose (CA); On-site; USD 185,000 - 240,000; Full time

Job summary

Astera Labs is seeking a Principal SerDes Bring-up Validation Engineer in San Jose, CA to lead end-to-end post-silicon bring-up, validation, and characterization. You will own bring-up strategies, translate requirements into test objectives, pass/fail criteria, and schedules while guiding hands-on lab work to verify silicon against specifications.

You will collaborate with AMS design, firmware, and system teams to build automated test frameworks, debug analog and digital interactions at the

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 8-12 years of hands-on experience in mixed-signal, high-speed lab environments with industry instruments (protocol analyzers, BERTs, real-time oscilloscopes, sampling scopes, TDRs, VNAs).
• Proven track record in post-silicon validation and bring-up of high-speed PHYs or retimers with understanding of physical layer and characterization flows.
• Deep understanding of NRZ and PAM4 architectures and high-speed building blocks (PLLs, CTLE, DFE, FFE, transmitter equalization).
• Strong programming ability in Python and C/C++ for test automation, data analysis, and firmware interaction.
• Excellent written and verbal communication.

Responsibilities

• Design, develop, and execute bring-up plans. Own end-to-end post-silicon bring up and characterization strategies.
• Drive design reviews and specification alignment to ensure testability and verification plans.
• Lead hands-on test execution and bring-up, including silicon block level testing and benchmarking.
• Build and maintain automation frameworks for scalable testing and data capture.
• Debug and optimize system performance across analog, digital, firmware, and protocol layers.
• Root cause cross-domain failures with lab measurements and waveform analysis.
• Collaborate with cross-functional teams to deliver detailed results and validation reports.
• Document findings and improve methodologies with formal characterization summaries.
• Develop test software and platform integrations using Python to configure and monitor multiple DSP and hardware platforms.
• Measure and communicate impact with data-driven conclusions to influence product direction.

Skills

Python

C/C++

Test automation

Data analysis

Troubleshooting

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, or related field

MS or PhD in Electrical Engineering

Tools

protocol analyzers

BERTs

oscilloscopes

sampling scopes

TDRs

VNAs

Job description

Astera Labs is seeking a Principal SerDes Bring-up Validation Engineer in San Jose, CA to lead end-to-end post-silicon bring-up, validation, and characterization. You will own bring-up strategies, translate requirements into test objectives, pass/fail criteria, and schedules while guiding hands-on lab work to verify silicon against specifications.

You will collaborate with AMS design, firmware, and system teams to build automated test frameworks, debug analog and digital interactions at the