Senior RTL Verification Engineer — FPGA & SystemVerilog Expert

Viasat; Carlsbad, Marlborough (CA, MA); On-site; USD 132,500 - 209,500; Full time

Benefits offered by this job

Comprehensive benefits package

Stock incentives

Medical Insurance

Job summary

Viasat is seeking a Design Verification Engineer to develop next-generation advanced communications products. Located in Carlsbad, CA, you will collaborate with engineers to verify RTL for secure communications systems.

The ideal candidate has a Bachelor’s in Electrical Engineering, 5+ years in hardware verification using SystemVerilog/UVM, and strong problem-solving skills. This position requires US citizenship and an active security clearance.

Competitive salary from $132,500 to $209,500 annually based on experience.

Qualifications

• 5+ years of experience in hardware verification using SystemVerilog/UVM.
• Proven success verifying complex RTL designs in industry-standard flows.
• Strong written and verbal communication skills.

Responsibilities

• Own the verification of custom RTL blocks and FPGA functionality.
• Work with RTL design engineers to define verification plans.
• Develop and maintain verification environment in SystemVerilog/UVM.

Skills

SystemVerilog/UVM

Hardware Verification

Digital Logic

Object Oriented Programming

Communication Skills

Education

Bachelor's Degree in Electrical Engineering or Computer Engineering

Tools

Siemens Questa

Cadence

Synopsys

Mentor

Job description

Viasat is seeking a Design Verification Engineer to develop next-generation advanced communications products. Located in Carlsbad, CA, you will collaborate with engineers to verify RTL for secure communications systems.

The ideal candidate has a Bachelor’s in Electrical Engineering, 5+ years in hardware verification using SystemVerilog/UVM, and strong problem-solving skills. This position requires US citizenship and an active security clearance.

Competitive salary from $132,500 to $209,500 annually based on experience.