Senior FPGA Engineer: Verilog, Verification Lead

VIAVI Solutions; Germantown (MD); Presencial; USD 96.000 - 178.000; Jornada completa

Descripción de la vacante

VIAVI Solutions invites a Senior FPGA Engineer to drive design, development, and verification of complex digital ICs for network test and measurement products. This role is based at our Germantown, MD facility.

You will architect high-performance blocks in Verilog/SystemVerilog, work with cross‑functional teams, and perform full lifecycle efforts from concept to characterization, including synthesis and timing analyses.

Formación

• Bachelor's or Master's in Electrical/Computer Engineering or related field.
• 3+ years in digital FPGA design and verification.
• Proficiency in Verilog/SystemVerilog for RTL design.
• Experience with standard EDA tools for synthesis and simulation.
• Expertise in advanced verification methodologies (UVM).
• Strong memory interface knowledge (DDR, PCIe).
• Scripting in Python/Perl/Tcl for automation.
• Excellent problem-solving and collaboration skills.

Responsabilidades

• Architect, design, and implement high‑performance digital blocks and subsystems.
• Collaborate with software, analog, and FPGA engineers to define specs and integrate designs.
• Participate in all FPGA lifecycle stages from concept to bring-up and characterization.
• Perform synthesis, STA, and power analysis to meet constraints and optimize performance.
• Contribute to design-methodology improvements and mentor junior engineers.

Conocimientos

Verilog/SystemVerilog

FPGA design

UVM

Memory interfaces

Python

Perl

Tcl

Scripting

Educación

Bachelor's or Master's in Electrical/Computer Engineering

Herramientas

EDA tools (synthesis & simulation)

Descripción del empleo

VIAVI Solutions invites a Senior FPGA Engineer to drive design, development, and verification of complex digital ICs for network test and measurement products. This role is based at our Germantown, MD facility.

You will architect high-performance blocks in Verilog/SystemVerilog, work with cross‑functional teams, and perform full lifecycle efforts from concept to characterization, including synthesis and timing analyses.