Senior RTL Engineer, SoC/CPU IP — Stock & Benefits

Apple Inc.; Cupertino (CA); On-site; USD 150,000 - 225,000; Full time

Benefits offered by this job

Medical and dental coverage

Employee stock purchase plan

Relocation assistance

Education reimbursement

Job summary

Apple Inc. in Cupertino, California, is seeking an experienced hardware RTL design engineer.

You will work with leads and architecture teams to define microarchitecture and develop RTL blocks using SystemVerilog/Verilog, integrating IPs and optimizing for timing, power, and performance. You will contribute through front-end synthesis/STA, timing closure, and collaboration across multidisciplinary groups to ensure on-time delivery and high-quality silicon.

Qualifications

• Master’s degree or foreign equivalent in Electrical Engineering or related field with 2 years of experience.
• 2 years of experience with SystemVerilog/Verilog RTL for CPU-based SoCs.
• Experience with CDC tools/techniques and multi-clock domains.
• RTL design experience with AMBA protocols (AHB).
• Experience with industry-standard simulation tools to verify/debug SoC or IP blocks.
• Configuring/integrating digital and analog IPs into an SoC/sub-system.
• Analyzing timing and resolving timing violations at digital-analog interfaces.
• Using lint tools to ensure RTL coding meets industry guidelines.
• Validating and debugging system silicon during chip bring-up.

Responsibilities

• Define the design microarchitecture with leads and architecture teams.
• Develop RTL design of blocks following architecture spec.
• Own RTL development/design and integrate shared IP blocks.
• Optimize memories and hard macros for the block.
• Complete front-end synthesis/STA to meet timing.
• Collaborate with multidisciplinary groups to ensure timely, high-quality delivery.
• Support timing, power, and performance optimization throughout the flow.
• Note: relocation may be available.

Skills

SystemVerilog / Verilog RTL

CDC tools / clock-domain techniques

AMBA / AHB RTL design

industry-standard simulation tools

digital and analog IP integration

timing analysis / STA

RTL linting standards

chip bring-up debugging

Education

Master’s degree in Electrical Engineering

Tools

SystemVerilog

Verilog

Job description

Apple Inc. in Cupertino, California, is seeking an experienced hardware RTL design engineer.

You will work with leads and architecture teams to define microarchitecture and develop RTL blocks using SystemVerilog/Verilog, integrating IPs and optimizing for timing, power, and performance. You will contribute through front-end synthesis/STA, timing closure, and collaboration across multidisciplinary groups to ensure on-time delivery and high-quality silicon.