Contract Hardware Design Engineer

Oho Group; Austin (TX); On-site; USD 96,000 - 179,000; Part time

Job summary

The Oho Group is partnering with an exciting AI hardware company in Austin, TX, seeking contract hardware engineers to push first-generation silicon. You will develop RTL for AI-focused subsystems and optimize datapaths, memory, and performance.

Responsibilities include leading synthesis, timing closure, and frontend verification, plus HW/SW co-optimization with architecture teams for AI workloads. 5+ years in silicon/ASIC frontend design and strong Verilog/SystemVerilog skills are required.

Qualifications

• 5+ years in silicon/ASIC frontend design.
• Strong RTL expertise in Verilog/SystemVerilog.
• Experience with synthesis, timing analysis, verification, and power optimization.
• Deep understanding of PPA trade-offs and memory bandwidth optimization (SRAM).
• Proficiency with EDA tools including Verilator, Yosys, and OpenSTA.

Responsibilities

• Develop and optimize RTL for AI centric hardware subsystems.
• Implement micro-architectures focused on datapaths, memory, and performance.
• Drive PPA optimization across frequency, power, and area targets.
• Lead synthesis, timing closure, and frontend verification.
• Collaborate with architecture teams on HW/SW co-optimization for AI workloads.

Skills

Silicon/ASIC frontend design

RTL (Verilog/SystemVerilog)

Synthesis & timing analysis

Power optimization

Memory bandwidth optimization

Tools

Verilator

Yosys

OpenSTA

Job description

The Oho Group have partnered with an exciting comapny in the AI space looking for contract hardware engineers to push them to first-generation silicon.

Responsibilities

• Develop and optimize RTL for AI centric hardware subsystems
• Implement micro-architectures focused on datapaths, memory, and performance
• Drive PPA optimization across frequency, power, and area targets
• Lead synthesis, timing closure, and frontend verification
• Collaborate with architecture teams on HW/SW co-optimization for AI workloads

Requirements

• 5+ years in silicon/ASIC frontend design
• Strong RTL expertise in Verilog/SystemVerilog
• Experience with synthesis, timing analysis, verification, and power optimization
• Deep understanding of PPA trade-offs and memory bandwidth optimization (SRAM)
• Proficiency with EDA tools including Verilator, Yosys, and OpenSTA