Senior Reliability Engineer – PDK, TFM

Jobtailor; Arizona; On-site; USD 120,000 - 180,000; Full time

Job summary

Jobtailor in the United States (Arizona) seeks a senior reliability engineer to define PDK design rules, create collateral, and lead reliability verification for advanced IP/SoC projects.

You will collaborate with internal teams and EDA vendors to enable PDK development, drive tool/flow enablement, and deliver TFMs and IP ecosystems while pushing quality enhancements and efficiency initiatives.

Qualifications

• 6+ years of experience in PDK development or reliability validation
• 3+ years in PDK development, reliability tool/flow, or EDA tool development
• Strong written and verbal communication and presentation skills
• Passion for quality and attention to detail and procedures
• Demonstrated capability to drive quality enhancements projects
• Team player with ability to work in diverse multi-cultural environments
• Flexibility and adaptability to ensure program commitments are met on time
• Hands-on experience on PDK development and validation
• Knowledge of PDK fundamentals, reliability design rules, and their implementation in PDK and TFM
• Capability to use AI or programming skills to write code, agents, or scripts for design rule, techfile generation, and quality assurance
• Experience with PDK, EDA tool/flow development, design flow application, and IP/SoC design validation and sign-off
• Experience in design impact and risk assessment in reliability areas
• Experience and knowledge of reliability verification and physics, including aging, BTI, HCI, electromigration, high-voltage design, EOS, and ESD
• Experience and skills in program management and stakeholder management

Responsibilities

• Define and generate reliability-related PDK design rules and collateral
• Conduct QA and benchmarking analysis
• Drive EDA tool and flow enablement with PDK development
• Collaborate with internal partners and EDA vendors to deliver TFM for design reliability verification
• Conduct competitive analysis and benchmark technology reliability
• Plan and deliver PDK, design rules, design collateral, TFM, and IP ecosystems
• Enable internal and external customer design on Intel technology
• Drive quality enhancement projects and efficiency initiatives

Skills

Reliability Design Rules

Circuit Design

IP Design

SoC Design Validation

Techfile Generation

Programming Skills

Design Impact Assessment

Reliability Verification

Physics Of Reliability

Quality Enhancement Projects

Education

Bachelor's degree in Electrical Engineering, Physics or related field

Master's degree or PhD considered

Tools

EDA Tools

Flow Development

Scripting/Programming

Job description

• Define and generate reliability-related PDK design rules and collateral covering reliability mechanisms


• Conduct quality assurance and benchmarking analysis


• Drive EDA tool and flow enablement in synergy with PDK development


• Work with internal partners and EDA vendors to deliver competitive TFM for design reliability verification


• Conduct competitive analysis and benchmark technology reliability


• Plan and deliver PDK, design rules, design collateral, TFM, and IP ecosystems


• Enable internal and external customer design on Intel technology


• Drive quality enhancement projects and efficiency and innovation initiatives

Requirements

• Bachelor's degree in electrical engineering, physics or a related field and 6+ years of relevant work experience, or 4+ years of relevant experience and a master's degree, or a PhD degree with 2+ years of relevant experience


• 3+ years' experience in PDK development, reliability tool and flow, design for reliability, circuit, IP and SoC design reliability validation using PDK, or EDA tool and flow development


• Excellent written and verbal communication and presentation skills


• Passion for quality and attention to details and procedures


• Demonstrated capability to drive quality enhancements projects


• Strong team player with ability to work in diverse multi-cultural environments


• Flexibility and adaptability to ensure program commitments are met on time


• Hands-on experience on PDK development and validation


• Knowledge and understanding of PDK fundamentals, reliability design rules, and their implementation in PDK and TFM


• Capability to use AI or programming skills to write code, agents, or scripts for design rule, techfile generation, and quality assurance


• Experience with PDK, EDA tool/flow development, design flow application, and IP and SoC design validation and sign-off


• Experience in design impact and risk assessment in reliability areas


• Experience and knowledge of reliability verification and physics, including aging, BTI, HCI, electro-migration, high-voltage design, EOS, and ESD


• Experience and skills in program management and stakeholder management

Core Competencies

Demonstrates expertise in PDK development, reliability design rules, and EDA tool and flow development, with a strong focus on quality assurance and design reliability validation. Capable of driving quality enhancement projects and collaborating effectively in diverse environments.

Highest-signal resume keywords

• PDK Development


• Reliability Tool And Flow


• Design For Reliability


• Quality Assurance


• EDA Tool Development

Hard Skills

• Reliability Design Rules


• Circuit Design


• IP Design


• SoC Design Validation


• Techfile Generation


• Programming Skills


• Design Impact Assessment


• Reliability Verification


• Physics Of Reliability


• Quality Enhancement Projects

Soft Skills

• Excellent Communication Skills


• Team PlayerFlexibility


• Attention To Detail


• Adaptability

Industry Keywords

• Reliability Mechanisms


• Benchmarking Analysis


• TFM


• IP EcosystemsAging


• BTI


• HCI


• Electro-Migration


• High-Voltage Design


• EOS

Tools & Technologies

• EDA Tools


• Design Flow Applications


• Reliability Verification Tools


• Quality Assurance Tools