Senior Principal RTL-to-GDS Solutions Engineer

Cadence; Austin (TX); On-site; USD 140,000 - 220,000; Full time

Job summary

Cadence in Austin is seeking a Senior Principal Solutions Engineer to champion RTL-to-GDS implementation for chip designers, focusing on Place and Route, Synthesis, STA/SDC, and tapeout support. The role involves deep technical work and effective communication with customers, plus ongoing training in Cadence tools.

You will own block and top-level implementations, lead design method discussions, run front-end evaluations, and help customers differentiate Cadence offerings through benchmarks

Qualifications

• 7+ years experience with ASIC design and Cadence/Synopsys PnR tools.
• Experience with Verilog and hardware description languages.
• Experience with physical synthesis, CTS, and STA for RTL-to-GDS flows.
• Experience designing with low power and multi-voltage techniques.
• Ability to lead customer evaluations and benchmarks.

Responsibilities

• Support RTL-to-GDS implementation flows end-to-end.
• Own block and top-level implementation and signoff efforts.
• Benchmark on CPUs, GPUs, and DSP cores.
• Collaborate with customers to showcase Cadence tool methodologies and success.

Skills

Verilog

Synthesis

Place and Route

STA/SDC

Low Power Design

Multi-Voltage Design

Clock Tree Debugging

Tools

Encounter Digital Implementation Platform

Cadence Front-end Solutions

Synopsys PnR Tools

Job description

Cadence in Austin is seeking a Senior Principal Solutions Engineer to champion RTL-to-GDS implementation for chip designers, focusing on Place and Route, Synthesis, STA/SDC, and tapeout support. The role involves deep technical work and effective communication with customers, plus ongoing training in Cadence tools.

You will own block and top-level implementations, lead design method discussions, run front-end evaluations, and help customers differentiate Cadence offerings through benchmarks