Senior Principal Solutions Engineer - RTL to GDSII Expert

Cadence; Austin (TX); On-site; USD 140,000 - 190,000; Full time

Job summary

Cadence is seeking a Senior Principal Solutions Engineer to accelerate adoption of Cadence products for chip designer customers. The role focuses on synthesis, place and route, and STA/SDC expertise to meet design PPA goals across RTL to GDSII delivery.

Expect hands-on experience with block and top-level implementation, signoff activities, and benchmarking on CPUs/GPUs/DSP cores. Collaboration with customers to articulate design methodologies using Cadence tools is essential.

Qualifications

• 7+ years of experience with Cadence products and ASIC design
• Design experience with ASIC using Verilog
• Experience with front-end/physical flow tools (P&R, CTS, STA/SDC)
• Experience in low power and multi-voltage design techniques
• RTL-to-GDSII delivery experience

Responsibilities

• Own block and top-level implementation and signoff focused efforts.
• Support RTL-to-GDSII delivery using Cadence tools and methodologies.
• Benchmark complex blocks across CPUs/GPUs/DSP cores with customers.
• Articulate design methodologies to customers and drive adoption.

Job description

Cadence is seeking a Senior Principal Solutions Engineer to accelerate adoption of Cadence products for chip designer customers. The role focuses on synthesis, place and route, and STA/SDC expertise to meet design PPA goals across RTL to GDSII delivery.

Expect hands-on experience with block and top-level implementation, signoff activities, and benchmarking on CPUs/GPUs/DSP cores. Collaboration with customers to articulate design methodologies using Cadence tools is essential.