RTL-to-GDS implementation, Senior Principal Solutions Engineer

Cadence; Austin (TX); On-site; USD 140,000 - 190,000; Full time

Job summary

Cadence is seeking a Senior Principal Solutions Engineer to accelerate adoption of Cadence products for chip designer customers. The role focuses on synthesis, place and route, and STA/SDC expertise to meet design PPA goals across RTL to GDSII delivery.

Expect hands-on experience with block and top-level implementation, signoff activities, and benchmarking on CPUs/GPUs/DSP cores. Collaboration with customers to articulate design methodologies using Cadence tools is essential.

Qualifications

• 7+ years of experience with Cadence products and ASIC design
• Design experience with ASIC using Verilog
• Experience with front-end/physical flow tools (P&R, CTS, STA/SDC)
• Experience in low power and multi-voltage design techniques
• RTL-to-GDSII delivery experience

Responsibilities

• Own block and top-level implementation and signoff focused efforts.
• Support RTL-to-GDSII delivery using Cadence tools and methodologies.
• Benchmark complex blocks across CPUs/GPUs/DSP cores with customers.
• Articulate design methodologies to customers and drive adoption.

Job description

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

The primary focus of Senior Principal Solutions Engineer is to support the adoption of Cadence Products to help Chip Designer Customers achieve superior performance for their Design PPA Goals. AE's are expected to possess Synthesis (logical and physical), Place and Route (primary focus) , STA / SDC skills and some experience supporting tapeouts. Experience with multivoltage design implementation and clock tree debugging is desirable.

In addition, Solutions Engineers are expected to be able to articulate design methodologies involving Cadence tools and be 'elevator talk' proficient in the full Cadence tool portfolio. Development time will be spent gaining expertise in additional, or specialization tools, broadening focus from product emphasis to methodology, Full Flow Implementation Training, and learning to leverage success . Full Flow Services Projects involves owning block implementation, top level implementation and Signoff focused efforts. Job exposure will be on RTL to GDSII delivery of projects. There's an opportunity to get involved in competitive benchmarking on complex blocks including CPUs, GPUs and DSP cores. These projects involve implementation in multiple technology nodes on standard foundry solutions. If you are looking to gain experience in methodology, product delivery, and working on cutting edge technology, this is the right role for you.

Position Requirements

• 7+ years experience and a strong technical knowledge of company products.
• Design experience should include ASIC design using industry-standard hardware description languages (Verilog)
• Senior Level Applications Engineer position with Deep Cadence or Synopsys place and route tool knowledge (Physical Synthesis, PnR, CTS, Static Timing Analysis) experience and knowledge are required
• Innovate with Low Power and Multi-Voltage Design Techniques working with leading edge Wireless and Mobile Customers
• Senior level Design Engineer position supporting RTL-to-GDS implementation flows using Encounter Digitial Implementation Platform
• Manage strategic customer evaluations/benchmarks on Cadence's front-end solutions to establish technology differentiation and assert Cadence competitive advantages. Multiplex several issues and set priorities and exploit new technologies are essential for success in the position

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