Senior/Principal High-Speed Analog Layout Engineer

Celero Communications, Inc.; United States; Remote; USD 200,000 - 250,000; Full time

Job summary

Celor Communication Inc. is seeking a Senior/Principal High-Speed Analog Layout Design Engineer in Irvine, CA to drive the layout of ADCs, DACs, PLLs and other high-performance blocks. You will collaborate with circuit designers and CAD/PDK teams to ensure first-pass silicon success.

The role leads layout development and reviews, mentors junior engineers, and contributes to automation initiatives while supporting cross-functional and international teams in a fast-paced startup environment.

Qualifications

• 10+ years in analog/mixed-signal layout in CMOS/FinFET tech.
• Experience delivering IP layout macros or full-chip layouts.
• Leadership in owning major IP layouts or blocks.
• Familiarity with TSMC FinFET nodes (N3/N5/N7/N16).

Responsibilities

• Lead physical layout of complex analog/mixed-signal macros from floor planning to verification.
• Collaborate with schematic designers to optimize performance, matching and reliability.
• Mentor junior layout engineers and contractors across time zones.
• Perform LVS, DRC, PERC, ERC checks and signoffs with industry tools.
• Contribute to chip-level planning, floor planning and power grid design.
• Lead layout reviews and ensure quality, verification completeness, and schedule adherence.
• Support automation through scripting and tool customization (SKILL, TCL, Python).

Skills

Analog/mixed-signal layout

CMOS/FinFET physics

IP/layout macro ownership

Floor planning

Hierarchical design

Routing and power grid design

Layout verification (LVS/DRC)

Layout optimization for matching/noise

Collaboration with international teams

Documentation and communication

Tools

Cadence Virtuoso

Calibre

Pegasus

Job description

Celor Communication Inc. is seeking a Senior/Principal High-Speed Analog Layout Design Engineer in Irvine, CA to drive the layout of ADCs, DACs, PLLs and other high-performance blocks. You will collaborate with circuit designers and CAD/PDK teams to ensure first-pass silicon success.

The role leads layout development and reviews, mentors junior engineers, and contributes to automation initiatives while supporting cross-functional and international teams in a fast-paced startup environment.