Senior Principal FPGA Engineer – Avionics & HDL Innovation

Northrop Grumman; San Diego (CA); On-site; USD 114,000 - 171,000; Full time

Benefits offered by this job

Relocation assistance

Travel 10% of the time

Job summary

Northrop Grumman Aeronautics Systems in Rancho Bernardo, CA seeks a Sr. Principal FPGA Design Engineer to design, implement and verify HDL for embedded avionics computers in a new product line.

You will work with a cross-functional team to translate requirements into FPGA hardware, firmware and software interfaces. Responsibilities include developing synthesizable HDL, implementing interfaces such as PCIe, SPI, I2C, UART, Ethernet, building comprehensive test benches, and performing functional

Qualifications

• Bachelor’s degree in a STEM discipline with 8 years related experience or higher degrees with fewer years
• Digital circuit design experience, including HDL, simulation, and test
• Hands-on prototyping and debugging of digital subsystems with FPGAs
• Experience with AMD FPGAs and the Vivado tool (or equivalent)

Responsibilities

• Define FPGA architecture and logic to support avionics computer functions
• Translate requirements to FPGA design specs and drive HW/SW interfaces
• Develop synthesizable HDL and implement PCIe, SPI, I2C, UART, Ethernet
• Create test benches, perform functional and timing simulations
• Support hardware-in-the-loop and system integration testing

Skills

FPGA design experience

Digital circuit design

Prototyping & debugging

OVM/UVM verification

Education

Bachelor's degree in STEM

Master's or PhD in STEM

Tools

Vivado

Job description

Northrop Grumman Aeronautics Systems in Rancho Bernardo, CA seeks a Sr. Principal FPGA Design Engineer to design, implement and verify HDL for embedded avionics computers in a new product line.

You will work with a cross-functional team to translate requirements into FPGA hardware, firmware and software interfaces. Responsibilities include developing synthesizable HDL, implementing interfaces such as PCIe, SPI, I2C, UART, Ethernet, building comprehensive test benches, and performing functional