Sr. Principal Electrical Engineer (FPGA Design Engineer)

0090 CORP-Corporate Office; United States; On-site; USD 114,000 - 171,000; Full time

Benefits offered by this job

Health insurance

Life and disability insurance

Savings plan

Paid holidays and PTO

Job summary

Northrop Grumman in Rancho Bernardo, CA is seeking a Sr. Principal FPGA Design Engineer to support the Common Products Circuit Design organization.

You will design, implement and verify HDL for avionics computer functions, collaborate with hardware, firmware and software teams, and drive synthesis, timing closure and verification across the product lifecycle.

The role requires a STEM degree and 8+ years, experience with Vivado, AMD FPGAs, and UVM, and the ability to obtain US Secret Clearance.

Qualifications

• Bachelor’s degree in a STEM discipline with 8+ years of related engineering experience OR Master’s with 6+ years OR PhD with 4+ years.
• Digital circuit design experience, including simulation & schematic capture through test and integration.
• Hands-on prototyping and debug with FPGAs and embedded processors; high-speed interfaces.
• Experience with AMD FPGAs and the Vivado tool (or equivalents).
• Experience with OVM/UVM verification methodologies.
• Ability to obtain and maintain US Government Secret Clearance.

Responsibilities

• FPGA Architecture and design to support avionics computer functions.
• Translate system requirements to FPGA requirements and design specs.
• HDL coding & implementation in collaboration with hardware, firmware and software teams.
• Create test benches and verification environments; perform timing and synthesis simulations.
• Support timing closure, resource optimization and documentation of findings.

Skills

FPGA Architecture & Design

Digital circuit design

Vivado tool

OVM/UVM verification

US Secret Clearance eligibility

Education

Bachelor's degree in STEM

Master's degree in STEM

PhD in STEM

Tools

AMD FPGAs

Vivado

Job description

RELOCATION ASSISTANCE: Relocation assistance may be available CLEARANCE REQUIRED FOR START: No CLEARANCE TYPE: Secret TRAVEL: Yes, 10% of the Time Description At Northrop Grumman, our employees have incredible opportunities to work on revolutionary systems that impact people's lives around the world today, and for generations to come. Our pioneering and inventive spirit has enabled us to be at the forefront of many technological advancements in our nation's history - from the first flight across the Atlantic Ocean, to stealth bombers, to landing on the moon. We look for people who have bold new ideas, courage and a pioneering spirit to join forces to invent the future, and have fun along the way. Our culture thrives on intellectual curiosity, cognitive diversity and bringing your whole self to work — and we have an insatiable drive to do what others think is impossible. Our employees are not only part of history, they're making history.

Northrop Grumman Aeronautics Systems is seeking a Sr. Principal FPGA Design Engineer to support the Common Products Circuit Design organization in Rancho Bernardo, CA. As FPGA Design Engineer you will design, implement and verify HDL to manage I/O devices on embedded computers in a new avionics’ product line. In collaboration with the product architect, electrical designers, software engineers and systems engineers you will develop requirements, define HW/SW interfaces and determine verification approaches. You will establish integrated product development workflows, processes and tools to reduce time to market for our safety critical avionics designs.

Essential Functions:

• FPGA Architecture & Design Define FPGA architecture and logic design to support avionics computer functions
• Translate system and board-level requirements to detailed FPGA requirements and design specifications
• Collaborate with the Product Architect to partition system functionality between hardware, firmware and software HDL Coding & Implementation
• Simulation, Verification and Validation Create comprehensive test benches and simulation environment to verify FPGA functionality Perform functional, timing and synthesis-level simulations to ensure deterministic and reliable operation Support hardware-in-the-loop and system-level integration testing with embedded processors and avionics systems Participate in formal verification and validation activities
• Synthesis, Place & Route, and Timing Closure Perform synthesis, implementation and timing closure using Vivado Optimize resource utilization, power consumption, and performance through iterative design and analysis Generate and review timing constraints to ensure reliable performance across all environmental conditions
• Provide support in person and through documentation generation of findings

Basic Qualifications:

• Bachelor’s degree in a STEM discipline with 8 years of related engineering experience; OR Master’s degree in a STEM discipline with 6 years of related experience; OR PhD in a STEM discipline with 4 year of related experience
• Digital circuit design experience, including simulation & schematic capture through test and integration
• Prior hands-on prototyping and debug experience testing complex digital subsystems, such as complex circuit card development involving FPGAs, and/or embedded processors, and/or high-speed interfaces
• Experience with AMD FPGAs and the Vivado tool (or equivalent tools)
• Experience with OVM/UVM Verification methodologies
• Ability to obtain and maintain US Government Secret Clearance
• Ability to obtain and maintain Program Access within a reasonable period of time, as determined by the Company

Preferred Qualifications:

• Experience facilitating internal and customer collaboration to capture and enhance engineering artifacts
• Demonstrated experience with the full product life cycle (requirements, design, implementation, and test)
• Demonstrated ability to translate system performance and operational specifications into hardware requirements, design, and test specifications

Primary Level Salary Range: $114,000.00 - $171,000.00 The above salary range represents a general guideline; however, Northrop Grumman considers a number of factors when determining base salary offers such as the scope and responsibilities of the position and the candidate's experience, education, skills and current market conditions.

Depending on the position, employees may be eligible for overtime, shift differential, and a discretionary bonus in addition to base pay.

Annual bonuses are designed to reward individual contributions as well as allow employees to share in company results.

Employees in Vice President or Director positions may be eligible for Long Term Incentives.

In addition, Northrop Grumman provides a variety of benefits including health insurance coverage, life and disability insurance, savings plan, Company paid holidays and paid time off (PTO) for vacation and/or personal business.

The application period for the job is estimated to be 20 days from the job posting date. However, this timeline may be shortened or extended depending on business needs and the availability of qualified candidates.

Northrop Grumman is an Equal Opportunity Employer, making decisions without regard to race, color, religion, creed, sex, sexual orientation, gender identity, marital status, national origin, age, veteran status, disability, or any other protected class. For our complete EEO and pay transparency statement, please visit http://www.northropgrumman.com/EEO.

U.S. Citizenship is required for all positions with a government clearance and certain other restricted positions.

We are a pioneering company. With careers across all areas: air, cyber, land, sea and space – our 90,000 employees work as one to defend and define the future. Northrop Grumman careers and internships are as varied as your interests, with a lifetime of potential that will give you every opportunity to do your best work.

Working together with people from many backgrounds, personal passions and disciplines, we share a drive to push the boundaries of science, technology and engineering to meet the ever evolving needs of our customers worldwide.