Senior FPGA Design Engineer – Avionics & HDL

Northrop Grumman; United States; On-site; USD 114,000 - 171,000; Full time

Benefits offered by this job

Relocation assistance

Health insurance

Life and disability insurance

Savings plan

Paid holidays and PTO

Job summary

Northrop Grumman Aeronautics Systems in Rancho Bernardo, CA seeks a Principal FPGA Design Engineer to design, implement and verify HDL for avionics computer I/O devices in a new product line. You will collaborate with architects, electrical designers, software and systems engineers to define HW/SW interfaces and verification strategies.

Responsibilities include synthesizable HDL coding, PCIe/SerDes interfaces, test benches, and timing closure to ensure robust performance across environments.

Qualifications

• Bachelor’s degree in a STEM discipline with 5 years of related engineering experience.
• Digital circuit design experience, including simulation & schematic capture.
• Experience with FPGAs and embedded processors with high-speed interfaces.

Responsibilities

• Define FPGA architecture and logic design to support avionics computer functions.
• Translate system and board-level requirements to detailed FPGA requirements and design specifications.
• Develop synthesizable HDL code for FPGA-based designs.
• Create test benches and simulation environments to verify FPGA functionality.
• Perform timing and synthesis-level simulations for reliable operation.
• Support hardware-in-the-loop and system integration testing.
• Contribute to timing constraints and design optimization.

Skills

FPGA design

HDL coding

verification methodologies

embedded interfaces

high-speed interfaces

Education

Bachelor’s degree in STEM

Tools

Vivado

AMD FPGAs

Job description

Northrop Grumman Aeronautics Systems in Rancho Bernardo, CA seeks a Principal FPGA Design Engineer to design, implement and verify HDL for avionics computer I/O devices in a new product line. You will collaborate with architects, electrical designers, software and systems engineers to define HW/SW interfaces and verification strategies.

Responsibilities include synthesizable HDL coding, PCIe/SerDes interfaces, test benches, and timing closure to ensure robust performance across environments.