Principal Design Engineer

Cadence Design Systems, Inc.; Cary (NC); On-site; USD 137,000 - 254,000; Full time

Job summary

Cadence Design Systems, Inc. is seeking a senior engineer to lead a team responsible for Palladium and Protium hardware-assisted verification for complex SOCs.

You will be implementing, verifying, and driving timing closure to tape-out SOCs, interfacing with frontend RTL and backend verification groups. The role requires deep experience with Cadence tools, RTL/SOC design, and advanced process nodes (5nm/3nm/2nm).

Qualifications

• BS degree in Electrical Engineering with a minimum of 7 years of experience
• MS with a minimum of 5 years of experience
• PhD with a minimum of 1 year of experience
• Experience with Cadence tools such as Innovus, Tempus, QRC, Voltus and Pegasus
• Knowledge of 5nm, 3nm and 2nm nodes

Responsibilities

• Lead a team to implement SOCs or sub system chips
• Work on RTL synthesis and floor planning
• Build clock trees and perform optimizations
• Close timing, IR drop and physical verification
• Review and document designs for taping out
• Interface with Front End RTL design teams and Back End Verification teams

Skills

RTL design & verification

Team leadership

Linux scripting

High-speed interfaces

Education

Bachelor's degree in Electrical Engineering

Master's degree

PhD

Tools

Innovus

Tempus

QRC

Voltus

Pegasus

Job description

SAN JOSE

CARY

Full time

R54892

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.

The Cadence Advantage

• The opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.

• Cadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.

• The unique “One Cadence – One Team” culture promotes collaboration within and across teams to ensure customer success

• Multiple avenues of learning and development available for employees to explore as per their specific requirement and interests

• You get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other—every day.

Job Responsibility

Palladium and Protium are high-capacitive, high-performance hardware assisted verification for complexed System-On-Chip (SOC). This role is to implement, verify, timing closure to tape out Palladium and Protium SOCs.

• Lead a team to implement SOCs or sub system chips

• Work on RTL synthesis and floor planning

• Build clock trees and perform optimizations

• Close timing, IR drop and physical verification

• Review and Document designs for taping out

• Interface with Front End RTL design teams and Back End Verification teams

Position Requirements/Qualifications:

• BS degree in Electrical Engineering with a minimum of 7 years of experience OR MS with a minimum of 5 years of experience OR PhD with a minimum 1 years of experience

• Experience with Cadence tools such as Innovus, Tempus, QRC, Voltus and Pegasus

• Experience with advanced technologies like 5nm, 3ns and 2nm nodes

• Experience using Linux servers, Script development using Shell/Perl/TCL

• Detailed knowledge about industry standard interfaces such as PCI Express, DDR, LPDDR, SRAM, UCIe, etc.

The annual salary range for California is $136,500 to $253,500. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.

We’re doing work that matters. Help us solve what others can’t.

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Cadence plays a critical role in creating the technologies that modern life depends on. We are a global electronic design automation company, providing software, hardware, and intellectual property to design advanced semiconductor chips that enable our customers create revolutionary products and experiences.

Thanks to the outstanding caliber of the Cadence team and the empowering culture that we have cultivated for over 25 years, Cadence continues to be recognized by Fortune Magazine as one of the 100 Best Companies to Work For. Our shared passion for solving the world’s toughest technical challenges, our dedication to pushing the limits of the industry, and our drive to do meaningful work differentiates the people of Cadence.

Cadence is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.

Cadence is committed to creating a diverse environment and is proud to be an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to race, color, sex, age, national origin, religion, sexual orientation, gender identity, status as a veteran, basis of disability, or any other protected class.