Senior Principal Analog IP Architect - Power & Clocking

onsemi; Allen (TX); Presencial; USD 140 000 - 180 000; Tempo integral

Resumo da oferta

onsemi is seeking an experienced Analog Design Engineer to contribute to power management and clocking IP blocks for the Treo Platform SoCs. You will lead detailed design, verification, and delivery of analog IP, collaborating with digital, validation, and CAD teams to enable tape-out and silicon validation.

This hands-on role requires 10+ years in analog IC design, deep knowledge of PM and clocking circuits, and proficiency in SPICE/AMS simulations.

Qualificações

• 10+ years of experience in analog IC design.
• Hands-on experience with power management and/or clocking circuits for SoCs.
• Solid understanding of device physics, analog architectures, and layout-dependent effects.
• Proficiency with SPICE/AMS simulation, variability analysis, and mixed-signal co-simulation.
• Ability to work independently on assigned blocks while communicating progress and risks clearly.

Responsabilidades

• Design, simulate, and verify power management IP including LDOs, DC/DC converters, and charge pumps.
• Design and implement clocking circuits such as PLLs, DLLs, oscillators, and clock distribution networks.
• Support IP architecture definition by contributing analysis, trade-off studies, and design proposals.
• Execute schematic design, layout guidance, post-layout extraction, and corner/Monte Carlo analysis to meet specifications.
• Deliver validated analog blocks into mixed-signal and digital-on-top subsystems for SoC integration.
• Collaborate with digital design, verification, PDK/technology, and validation teams to resolve integration issues.
• Participate in lab bring-up, silicon characterization, and post-silicon debug in partnership with validation and test engineers.
• Document designs, assumptions, and test results to support IP reuse and long-term platform quality.

Conhecimentos

Analog IC design

Power management

Clocking circuits

Device physics

Layout-dependent effects

SPICE/AMS simulations

Independent work

Ferramentas

Verilog-A/AMS/SV RNM modeling

Descrição da oferta de emprego

onsemi is seeking an experienced Analog Design Engineer to contribute to power management and clocking IP blocks for the Treo Platform SoCs. You will lead detailed design, verification, and delivery of analog IP, collaborating with digital, validation, and CAD teams to enable tape-out and silicon validation.

This hands-on role requires 10+ years in analog IC design, deep knowledge of PM and clocking circuits, and proficiency in SPICE/AMS simulations.