Sr Principal Engineer AI/ML

GlobalFoundries; California (MO); On-site; USD 171,000 - 325,000; Full time

Job summary

GlobalFoundries seeks an experienced CPU IP Design Engineer to lead RTL development of a high-performance AI-enabled RISC-V CPU core. You will drive micro-architecture, design critical blocks, and collaborate with modeling teams to optimize performance, power, and area.

The role covers verification strategy, design features refinement, and integration at the SoC level, requiring deep expertise in Verilog/SystemVerilog and vector/matrix CPU engines.

Qualifications

• Master’s with 10+ years of experience, PhD 5+ years of work experience.
• Hands-on knowledge of the pipeline stages of an in-order or out-of-order high-performance CPU core.
• Expertise in instruction fetch/decode, branch prediction, scheduling, ROB, out-of-order execution and vector/memory subsystems.

Responsibilities

• Drive the micro-architecture and design of critical blocks of the CPU core.
• Design of RISC-V Vector CPU core and its custom extensions.
• Design of AI-enabled Matrix engine to augment the Vector CPU.
• Explore high-performance strategies with the CPU modeling team.
• Configure RTL design features to meet power, performance, area, timing goals.
• Support functional verification and assist verification strategy.
• Assist with RTL performance verification and timing/power optimization.

Skills

CPU architecture

RISC-V

Vector CPU

Verilog/SystemVerilog

RTL design

Performance optimization

Python/Perl scripting

Digital design

Verification

Education

Master's degree in EE/CS

PhD (optional)

Tools

Verilog simulators

Waveform debugging tools

SoC integration tools

Job description

About GlobalFoundries

GlobalFoundries (GF) is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GF makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.

Summary of Role

We are seeking an experienced CPU IP Design Engineer. Responsible for Defining, leading and owning RTL development of our latest AI-enabled RISC-V CPU core. The candidate will be responsible for all aspects of the design including Functional Features, Performance, Power, and Area.

Essential Responsibilities

• Drive the micro-architecture and design of critical blocks of the CPU core
• Design of RISC-V Vector CPU core and its custom extensions
• Design of AI-enabled Matrix engine to augment the Vector CPU
• Explore high-performance strategies working with the CPU modeling team
• Perform Microarchitecture development and specification- from early high-level architectural exploration, through microarchitectural research and arrive at detailed specifications
• Configure Design Features Development, assessment, and refinement of RTL design to target power, performance, area, and timing goals
• Perform Functional verification support and assist in the design verification strategy
• Assist with the verification of RTL design performance goals
• Partner with a multi-functional engineering team to implement and validate physical design aspects of timing, area, reliability, testability, and power

Other Responsibilities

Perform all activities in a safe and responsible manner and support all Environmental, Health, Safety & Security requirements and programs.

Required Qualifications

• Hands-on working knowledge of the pipeline stages of an in-order or out-of-order high-performance CPU core
• Thorough knowledge of microprocessor architecture including expertise in one or more of the following areas:
• * Instruction fetch and decode, branch prediction techniques
• * Instruction scheduling, register renaming, Reorder Buffer (ROB)
• * Out-of-order execution
• * Integer and Floating-point execution
• * Load/Store execution
• * Instruction and Data Prefetch
• * Vector data path
• * Cache and memory subsystems
• Knowledge of Cache coherency and memory consistency
• Knowledge of System Verilog, Verilog and/or VHDL
• Experience with simulators and waveform debugging tools.
• Knowledge of logic design principles along with timing and power implications
• Master’s with 10+ years of experience, PhD 5+ years of work experience

Preferred Qualifications

• Experience with designing RISC-V, ARM, and/or MIPS CPU
• Experience with Hardware multi-threading, virtualization, and SIMD designs
• Experience with vector and matrix-enabled CPUs, preferably RISC-V processors.
• Understanding of high-performance techniques and trade-offs in a CPU microarchitecture
• Understanding of low-power microarchitecture techniques
• Experience using a scripting language such as Perl or Python
• Understanding of CPU integration at SoC level
• Understanding of Safety and Security microarchitecture

Expected Salary Range

$171,000.00 - $325,000.00

The exact Salary will be determined based on qualifications, experience and location.

If you need a reasonable accommodation for any part of the employment process, please contact us by email at [e-mail] and let us know the nature of your request and your contact information. Requests for accommodation will be considered on a case-by-case basis. Please note that only inquiries concerning a request for reasonable accommodation will be responded to from this email address.

An offer with GlobalFoundries is conditioned upon the successful completion of pre-employment conditions, as applicable, and subject to applicable laws and regulations.

GlobalFoundries is fully committed to equal opportunity in the workplace and believes that cultural diversity within the company enhances its business potential. GlobalFoundries goal of excellence in business necessitates the attraction and retention of highly qualified people. Artificial barriers and stereotypic biases detract from this objective and may be illegally discriminatory.

All policies and processes which pertain to employees including recruitment, selection, training, utilization, promotion, compensation, benefits, extracurricular programs, and termination are created and implemented without regard to age, ethnicity, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, sexual orientation, gender identity or expression, veteran status, or any other characteristic or category specified by local, state or federal law