Senior Power Systems Engineer — Low-Power Chipsets

Qualcomm; Austin (TX); On-site; USD 187,000 - 280,000; Full time

Job summary

Qualcomm Technologies, Inc. is seeking an experienced Chipset Power System Engineer to lead a cross-functional team in modeling SOC/chipset power and devising innovations to optimize hardware and software for low power consumption. The role spans all design stages to guide power-efficient end-to-end solutions.

The position involves architecture tradeoff analysis, customer interactions, and power modeling of customer-specific use cases to meet stringent power targets across Snapdragon chipsets.

Qualifications

• Master's degree in Electrical Engineering or equivalent is required.
• 15 years of professional experience in power, SOC, chipset, or platform design is preferred.
• Experience with analysis and design of low power features at SOC or chipset level.
• System level power modeling and analysis is essential.

Responsibilities

• Power architecture and tradeoff analysis.
• Chipset and system level power modeling, analysis and optimization for SOC and platform solutions.
• Identify power requirements and quantify power gap/risk areas.
• Optimize power efficiency and performance of present generation designs and help architect future products.
• Guide cross functional teams through the design cycle to meet power targets.
• Design of power features and collaboration with systems, software, hardware, silicon process, and production test teams.
• Advertise chipset capabilities to customers and address power requirements.
• Power modeling of customer-specific use cases and designs.

Skills

15 years experience

Power modeling

Low power design

System power analysis

Architecture knowledge

Education

Master's degree in Electrical Engineering

Job description

Qualcomm Technologies, Inc. is seeking an experienced Chipset Power System Engineer to lead a cross-functional team in modeling SOC/chipset power and devising innovations to optimize hardware and software for low power consumption. The role spans all design stages to guide power-efficient end-to-end solutions.

The position involves architecture tradeoff analysis, customer interactions, and power modeling of customer-specific use cases to meet stringent power targets across Snapdragon chipsets.