Senior PMIC Design Engineer for Power Management ICs

QUALCOMM, Inc.

Santa Clara (CA)

Hybride

USD 153 000 - 230 000

Plein temps

14 jours+

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Résumé du poste

Qualcomm Technologies, Inc. is seeking a senior PMIC design engineer in Santa Clara, CA to lead architecture, design, verification, and documentation of mixed-signal PMIC blocks for compute, data center, automotive, and industrial applications.

You will work with Cadence, SPICE, MATLAB and Verilog/VHDL, guide layout, drive silicon bring-up, characterization, and qualification, and mentor peers while aligning with product and validation teams.

Qualifications

6+ years of analog, mixed-signal or PMIC design experience.
MS/PhD preferred in Electrical Engineering.
Experience with Cadence, SPICE, MATLAB, or Verilog/VHDL.

Responsabilités

Execute architecture implementation, circuit design, and verification of PMIC blocks.
Own design and verification strategy for controller circuitry and high-current power stage interfaces.
Guide layout engineers and perform physical/reliability verification.
Run advanced checks across PVT and operating conditions.
Interpret simulation and silicon data to drive design actions.
Document design intent and silicon findings for PMIC subsystems.
Collaborate with validation, test, and product teams for silicon bring-up.
Stay updated with industry trends and apply insights to designs.
Provide mentorship and participate in design reviews.