Senior PMIC Design Engineer | Mixed-Signal Power ICs

QUALCOMM, Inc.

Tempe (AZ)

On-site

USD 131,000 - 197,000

Full time

5 days ago
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Job summary

Qualcomm Technologies, Inc. in Tempe, Arizona, is seeking a Staff PMIC Design Engineer to define, verify, and document Mixed Signal and/or Power Management ICs.

You will collaborate with cross-functional teams to deliver PMIC solutions across automotive, IoT, and cellular platforms. Minimum qualifications include a Bachelor's in Electrical Engineering with 6+ years of analog or PMIC design, or a Master's with 4+ years, or a PhD with 2+ years, plus 2+ years using Cadence, SPICE, MATLAB, or

Qualifications

  • Bachelor's degree in Electrical Engineering with 6+ years of analog, mixed-signal or PMIC design experience; OR Master's with 4+ years; OR PhD with 2+ years.
  • 2+ years of academic and/or work experience using CADENCE, SPICE, MATLAB, and/or Verilog/VHDL.

Responsibilities

  • Defines, designs, verifies, and documents critical Mixed Signal and/or Power Management ICs.
  • Determines critical architectural design and circuit level implementations based on system requirements.
  • Leverages knowledge of power electronics, control theory, precision oscillators, high accuracy data converters and analog front ends in design and verification.
  • Owns the design and verification strategies of PMICs.
  • Collaborates with layout engineers to generate circuit layouts and conduct physical verification.
  • Documents details circuit implementation, control, and testability for a PMIC or PMU.

Education

Bachelor's degree in Electrical Engineering
Master's degree in Electrical Engineering or related field
PhD in Electrical Engineering or related field

Tools

Cadence
SPICE
MATLAB
Verilog/VHDL

Job description

Qualcomm Technologies, Inc. in Tempe, Arizona, is seeking a Staff PMIC Design Engineer to define, verify, and document Mixed Signal and/or Power Management ICs.

You will collaborate with cross-functional teams to deliver PMIC solutions across automotive, IoT, and cellular platforms. Minimum qualifications include a Bachelor's in Electrical Engineering with 6+ years of analog or PMIC design, or a Master's with 4+ years, or a PhD with 2+ years, plus 2+ years using Cadence, SPICE, MATLAB, or

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