Senior PMIC Design Engineer – Power Management

Qualcomm

Santa Clara (CA)

On-site

USD 127,000 - 190,000

Full time

14 days+

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Job summary

Qualcomm Technologies, Inc. in Santa Clara, CA seeks an experienced IC Design Engineer to lead the definition, design, verification, and documentation of mixed-signal PMICs and high‑current power stage circuitry for compute, data center, automotive, and industrial applications.

You will own the design and verification strategy for PMIC subsystems, mentor engineers, and collaborate with validation and product teams to bring silicon from concept to production, using Cadence ADE, SPICE, MATLAB, and

Qualifications

Bachelor's degree in Electrical Engineering with 4+ years IC Design experience.
Master’s degree in Electrical Engineering or related field with 2+ years IC Design experience.
PhD in Electrical Engineering or related field.
2+ years of academic/work experience using CADENCE, SPICE, MATLAB, and/or Verilog/VHDL.

Responsibilities

Uses Cadence tools to implement architecture, design and verification of complex PMIC blocks.
Owns design and verification strategy for power management ICs and controller circuitry.
Guides layout engineers to generate high‑quality layouts and verifies circuits.
Runs advanced checks to ensure designs meet specifications across PVT conditions.
Interprets simulation, silicon data, and drives corrective design actions.
Documents design intent and silicon findings for PMIC subsystems.