Senior Physical Design (PNR) Engineer

Eximietas Design; San Francisco (CA); On-site; USD 180,000 - 260,000; Full time

Job summary

Eximietas Design is seeking a Senior Physical Design (PNR) Engineer to support advanced-node semiconductor programs (5nm/3nm). Roles span Floorplanning, Top-Level PNR/Integration, and Block-Level PNR implementation, with focus on timing, power and density targets for SoCs.

We value 10+ years of hands-on PD/PNR,Cadence Innovus expertise, and strong scripting skills. Locations: San Jose or San Diego preferred; other locations can be discussed in later stages.

Qualifications

• 10+ years of hands-on Physical Design / PNR experience.
• Strong proficiency with Cadence Innovus (required); exposure to Tempus/Voltus is a plus
• Familiarity with Synopsys ICC2 or Fusion Compiler (preferred but not mandatory)
• Deep understanding of advanced-node challenges (MCMM, OCV, SI, IR, EM, density)
• Strong scripting skills (Tcl, Python, Shell) for flow automation and debugging
• Ability to collaborate effectively across RTL, Architecture, Verification, and Signoff teams
• Experience working on 7nm / 5nm / 3nm nodes is a strong advantage
• Work on cutting-edge advanced-node semiconductor programs
• High-impact roles with strong technical ownership
• A collaborative, engineering-centric culture
• Competitive compensation and growth opportunities

Responsibilities

• Develop efficient, congestion-aware floorplans for blocks and top-level SoCs
• Own macro placement, pin assignment, and power grid planning
• Drive early feasibility for timing, IR, density, and overall PPA targets
• Lead top-level routing and physical integration across hierarchical designs
• Identify and resolve congestion, routing issues, and signoff-driven ECOs
• Ensure alignment and consistency across block owners and timing/signoff teams
• Achieve clean timing, DRC, and power results across MCMM scenarios
• Implement ECOs to optimise PPA and accelerate convergence at advanced nodes

Skills

Scripting (Tcl/Python/Shell)

Cross-functional collaboration

Strong technical ownership

Senior-level PD experience

Tools

Cadence Innovus

Tempus/Voltus

ICC2 / Fusion Compiler exposure

Job description

Senior Physical Design (PNR) Engineer – Multiple Roles

Locations: San Jose or San Diego preferred (other locations can be discussed)

Experience: 10+ years

Type: Full-Time

Eximietas Design is expanding its Physical Design team and hiring Senior PNR Engineers to support advanced-node (5nm/3nm) semiconductor programs. We are looking for engineers who bring strong technical ownership in Floorplanning, Top-Level Integration, or Block-Level PNR Implementation.

If you thrive on solving complex physical design challenges and want to help drive next-generation SoC designs, we want to talk to you.

Open Positions

We are hiring across three specialisation areas within Physical Design:

What You Will Do

Floorplanning

• Develop efficient, congestion-aware floorplans for blocks and top-level SoCs
• Own macro placement, pin assignment, and power grid planning
• Drive early feasibility for timing, IR, density, and overall PPA targets

Top-Level PNR / Integration

• Lead top-level routing and physical integration across hierarchical designs
• Identify and resolve congestion, routing issues, and signoff-driven ECOs
• Ensure alignment and consistency across block owners and timing/signoff teams

Block-Level PNR (Standard Cell Implementation)

• Achieve clean timing, DRC, and power results across MCMM scenarios
• Implement ECOs to optimise PPA and accelerate convergence at advanced nodes

What You Bring

• 10+ years of hands-on Physical Design / PNR experience
• Strong proficiency with Cadence Innovus (required); exposure to Tempus/Voltus is a plus
• Familiarity with Synopsys ICC2 or Fusion Compiler (preferred but not mandatory)
• Deep understanding of advanced-node challenges (MCMM, OCV, SI, IR, EM, density)
• Strong scripting skills (Tcl, Python, Shell) for flow automation and debugging
• Ability to collaborate effectively across RTL, Architecture, Verification, and Signoff teams
• Experience working on 7nm / 5nm / 3nm nodes is a strong advantage
• Work on cutting-edge advanced-node semiconductor programs
• High-impact roles with strong technical ownership
• A collaborative, engineering-centric culture
• Competitive compensation and growth opportunities