Physical Design Engineer

Programmers.io; Mountain View (CA); On-site; USD 120,000 - 170,000; Full time

Job summary

Programmers.io is seeking a skilled Physical Design Engineer for Mountain View, CA. This contract/full-time role requires 8+ years of chip design experience and hands-on work with high-speed designs and advanced technology nodes. You will push PPA limits and ensure sign-off readiness.

The position entails on-site work in Mountain View with responsibilities spanning floorplanning, CTS, routing, timing closure, and physical verification. Strong scripting and EDA tool experience are essential.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 3 to 8 years of hands-on chip design experience.
• Strong knowledge of Synopsys, Cadence, or Siemens EDA tools.
• Good scripting skills in Tcl, Perl, or Python.
• Deep understanding of sub-micron technology node.

Responsibilities

• Place and Route (PPR): Run full-chip and block-level floorplanning, placement, clock tree synthesis (CTS), and routing using industry tools.
• Timing Closure: Fix setup, hold, and DRC violations to meet tight timing goals.
• PPA Optimization: Balance power, performance, and area to meet product specs.
• Physical Verification: Run LVS, DRC, and antenna checks to ensure design manufacturing safety.
• Low Power Design: Implement multi-voltage and power-gating techniques.

Skills

Scripting: Tcl/Perl/Python

PPR/CTS/Timing concepts

Sub-micron tech understanding

Education

Bachelor’s or Master’s degree in Electrical Engineering or related field

Tools

Synopsys Cadence Siemens EDA

Job description

We need a skilled Physical Design Engineer to turn complex chip plans into real silicon. You will work on high-speed designs using advanced technology nodes. Your main job is to push PPA limits while ensuring complete sign-off readiness.

Title: Physical Design Engineer

Location: Onsite to Mountain View, CA

Duration: Contract/Full time

Experience:8+ Years

Key Responsibilities

• Place and Route (PPR): Run full-chip and block-level floorplanning, placement, clock tree synthesis (CTS), and routing using industry tools.
• Timing Closure: Fix setup, hold, and DRC violations to meet tight timing goals.
• PPA Optimization: Balance power, performance, and area to meet product specs.
• Physical Verification: Run LVS, DRC, and antenna checks to ensure design manufacturing safety.
• Low Power Design: Implement multi-voltage and power-gating techniques.

Requirements

• Bachelor’s or Master’s degree in Electrical Engineering or related field.
• 3 to 8 years of hands-on chip design experience.
• Strong knowledge of industry tools from Synopsys, Cadence, or Siemens EDA.
• Good scripting skills in Tcl, Perl, or Python.
• Deep understanding of sub-micron technology node