Senior Physical Design Engineer - VR/AR Silicon

Meta; Sunnyvale (CA); On-site; USD 146,000 - 209,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta's Reality Labs Silicon team is hiring a Physical Design Engineer to translate RTL designs into optimized silicon implementations, covering floorplanning, placement, CTS, routing, and sign-off for VR and AR chips in Sunnyvale.

You will collaborate with architecture, design, and verification teams to shape physical implementation strategy, drive power and performance targets, and contribute to internal flows, automation, and validation across process nodes.

Qualifications

• Bachelor’s degree in Computer Science, Computer Engineering, or equivalent practical experience.
• 6+ years of experience in physical design of complex digital ASICs or SoCs, including floorplanning, placement, CTS, routing, and sign-off.
• 6+ years of experience with static timing analysis and timing closure in advanced process nodes (7nm or below).
• Experience with industry-standard physical design EDA tools and physical verification flows including DRC, LVS, and antenna sign-off.

Responsibilities

• Lead physical implementation of complex blocks and subsystems from floorplanning through tapeout, including placement, clock tree synthesis, routing, and physical verification
• Define and drive physical design methodology, constraints, and flows to meet power, performance, and area targets for custom silicon in VR and AR products
• Perform static timing analysis and timing closure across multiple process corners and operating conditions
• Develop and optimize power delivery network strategies, including IR drop analysis and electromigration sign-off
• Collaborate with RTL designers and architects to provide physical design feedback that influences microarchitecture and floorplan decisions
• Partner with design verification and DFT teams to ensure physical implementation supports functional correctness and testability requirements
• Drive physical verification sign-off including DRC, LVS, and antenna checks in advanced process nodes
• Identify and resolve physical implementation bottlenecks related to congestion, timing, and power through iterative analysis and targeted optimization
• Contribute to the development and continuous improvement of internal physical design flows, scripts, and automation to increase team efficiency

Skills

Floorplanning

Placement

Clock Tree Synthesis

Routing

Sign-off

Static Timing Analysis

Power Delivery

Education

Bachelor's degree in Computer Science/Engineering or equivalent

Tools

Cadence Innovus

Synopsys ICC2

Fusion Compiler

PrimeTime

StarRC

Job description

Meta's Reality Labs Silicon team is hiring a Physical Design Engineer to translate RTL designs into optimized silicon implementations, covering floorplanning, placement, CTS, routing, and sign-off for VR and AR chips in Sunnyvale.

You will collaborate with architecture, design, and verification teams to shape physical implementation strategy, drive power and performance targets, and contribute to internal flows, automation, and validation across process nodes.