Senior Silicon Verification Engineer (AR/VR)

Meta; San Diego (CA); On-site; USD 146,000 - 209,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta Reality Labs is building custom silicon to power the next generation of AR/VR devices. As a Design Verification Engineer on the silicon team, you will verify complex chips from spec to tape-out, collaborating with design, architecture, and software teams to ensure functional correctness and quality in high-performance, low-power silicon.

You will own verification plans, implement constrained-random UVM testbenches, define functional coverage, and drive regression and formal verification

Qualifications

• 6+ years of experience in digital design verification.
• 6+ years of experience with hardware description languages (SystemVerilog/VHDL).
• Experience defining and closing functional coverage and code coverage models.

Responsibilities

• Develop and own verification plans for digital blocks and subsystems.
• Design and implement constrained-random UVM testbenches for RTL designs.
• Define and close functional coverage models and code coverage metrics.
• Collaborate with RTL designers to review microarchitecture specifications.
• Develop regression frameworks and automated test suites for CI.
• Perform formal verification and property checking.
• Debug failing simulations via waveform analysis and logs.
• Partner with post-silicon teams to develop pre-silicon test content.
• Contribute to reusable verification IP and shared infrastructure.
• Track progress, coverage, and risk for stakeholders.

Skills

UVM testbenches

SystemVerilog/VHDL

Python/Perl scripting

Functional coverage modeling

RTL debugging

Waveform analysis

Education

Bachelor's degree in Computer Science/Engineering

Job description

Meta Reality Labs is building custom silicon to power the next generation of AR/VR devices. As a Design Verification Engineer on the silicon team, you will verify complex chips from spec to tape-out, collaborating with design, architecture, and software teams to ensure functional correctness and quality in high-performance, low-power silicon.

You will own verification plans, implement constrained-random UVM testbenches, define functional coverage, and drive regression and formal verification