Physical Design Engineer, Reality Labs Silicon

Meta; San Diego (CA); On-site; USD 146,000 - 209,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta is seeking a Physical Design Engineer for Reality Labs Silicon in California. You will translate RTL into optimized silicon, leading floorplanning, placement, CTS, routing, and sign-off for VR/AR devices.

You will collaborate with architecture and verification teams to refine physical design strategies, drive power integrity analyses, and ensure robust sign-off across advanced nodes.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent practical experience.
• 6+ years of physical design experience in digital ASICs/SoCs.
• Experience with DRC/LVS and antenna checks in advanced nodes.

Responsibilities

• Lead physical implementation from floorplanning to tapeout, including placement and CTS.
• Define flows and constraints to meet power, performance, and area targets.
• Perform STA and timing closure across process corners and operating conditions.

Skills

Physical design

Static timing analysis

Power network

Python scripting

Tcl scripting

Education

Bachelor's degree in Electrical Engineering

Tools

Cadence Innovus

Synopsys ICC2

PrimeTime

Fusion Compiler

Job description

Meta's Silicon Engineering team is building custom silicon to power the next generation of virtual and augmented reality products, including VR headsets and AR glasses. As a Physical Design Engineer, you will translate RTL designs into optimized silicon implementations, working across floorplanning, placement, clock tree synthesis, routing, and signoff to deliver high-performance, power-efficient chips. In this role, you will collaborate closely with architecture, design, and verification teams to shape the physical implementation strategy for wearable and spatial computing devices that define the future of human connection.Physical Design Engineer, Reality Labs Silicon Responsibilities:Lead physical implementation of complex blocks and subsystems from floorplanning through tapeout, including placement, clock tree synthesis, routing, and physical verificationDefine and drive physical design methodology, constraints, and flows to meet power, performance, and area targets for custom silicon in VR and AR productsPerform static timing analysis and timing closure across multiple process corners and operating conditionsDevelop and optimize power delivery network strategies, including IR drop analysis and electromigration sign-offCollaborate with RTL designers and architects to provide physical design feedback that influences microarchitecture and floorplan decisionsPartner with design verification and DFT teams to ensure physical implementation supports functional correctness and testability requirementsDrive physical verification sign-off including DRC, LVS, and antenna checks in advanced process nodesIdentify and resolve physical implementation bottlenecks related to congestion, timing, and power through iterative analysis and targeted optimizationContribute to the development and continuous improvement of internal physical design flows, scripts, and automation to increase team efficiencyMinimum Qualifications:Bachelor's degree in Computer Science, Computer Engineering, relevant technical field, or equivalent practical experience6+ years of experience in physical design of complex digital ASICs or SoCs, including floorplanning, placement, CTS, routing, and sign-off6+ years of experience with static timing analysis and timing closure in advanced process nodes (7nm or below)Experience with industry-standard physical design EDA tools such as Cadence Innovus, Synopsys ICC2, or equivalentExperience with physical verification flows including DRC, LVS, and antenna sign-offExperience with power analysis and power delivery network implementation, including IR drop and electromigration analysisPreferred Qualifications:Experience with physical design implementation tools such as Synopsys Fusion Compiler (including FusionPilot/ConfigAI for run analysis and TCL configuration), Cadence Innovus, StarRC, and PrimeTimeExperience with physical design for low-power wearable or mobile SoCs, including multi-voltage domain and power gating implementationExperience developing and maintaining physical design automation scripts using Python or Tcl to improve implementation flowsFamiliarity with co-design methodologies that bridge RTL microarchitecture decisions and physical implementation constraintsExperience with advanced node process design kits (5nm or below) and associated physical design challengesAbout Meta:Meta builds technologies that help people connect, find communities, and grow businesses. When Facebook launched in 2004, it changed the way people connect. Apps like Messenger, Instagram and WhatsApp further empowered billions around the world. Now, Meta is moving beyond 2D screens toward immersive experiences like augmented and virtual reality to help build the next evolution in social technology. People who choose to build their careers by building with us at Meta help shape a future that will take us beyond what digital connection makes possible today—beyond the constraints of screens, the limits of distance, and even the rules of physics.Meta is proud to be an Equal Employment Opportunity and Affirmative Action employer. We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or other applicable legally protected characteristics. We also consider qualified applicants with criminal histories, consistent with applicable federal, state and local law. Meta participates in the E-Verify program in certain locations, as required by law. Please note that Meta may leverage artificial intelligence and machine learning technologies in connection with applications for employment.Meta is committed to providing reasonable accommodations for candidates with disabilities in our recruiting process. If you need any assistance or accommodations due to a disability, please let us know at [e-mail].$146,000/year to $209,000/year + bonus + equity + benefitsIndividual compensation is determined by skills, qualifications, experience, and location. Compensation details listed in this posting reflect the base hourly rate, monthly rate, or annual salary only, and do not include bonus, equity or sales incentives, if applicable. In addition to base compensation, Meta offers benefits. Learn more about benefits at Meta.