Lead Physical Design Engineer – VR/AR SoCs

Socket.dev; Sunnyvale (CA); On-site; USD 146,000 - 209,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Meta is seeking a Physical Design Engineer to translate RTL designs into optimized silicon implementations, covering floorplanning, placement, CTS, routing, and sign-off for high-performance VR/AR chips. You will collaborate with architecture, design, and verification teams to define physical implementation strategies for wearable devices.

The role requires 6+ years in physical design, expertise in timing closure, power integrity, and advanced node flows.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or related field
• 6+ years of physical design experience on complex digital ASICs/SoCs
• Experience with CTS, routing, DRC/LVS, and antenna sign-off
• Experience in 7nm or below process nodes and power integrity analysis

Responsibilities

• Lead physical implementation from floorplanning through tapeout including placement, CTS, routing, and physical verification
• Define and drive physical design flows to meet power, performance, and area targets for custom silicon in VR/AR
• Perform static timing analysis and timing closure across process corners
• Develop power delivery networks and IR drop analysis with electromigration sign-off
• Collaborate with RTL designers and architects to influence microarchitecture and floorplan decisions
• Support DFT commitments and ensure sign-off readiness with verification teams
• Drive physical verification sign-off including DRC, LVS, and antenna checks in advanced nodes
• Identify and resolve bottlenecks related to congestion, timing, and power via iterative optimization
• Contribute to internal physical design flows, scripts, and automation to improve efficiency

Skills

Physical design execution

Floorplanning & CTS

Static timing analysis

Power delivery network

RTL/architecture collaboration

DFT & sign-off

Python/Tcl scripting

Education

Bachelor's degree in CS/CE or equivalent

Tools

Cadence Innovus

Synopsys ICC2

Fusion Compiler

StarRC

PrimeTime

Job description

Meta is seeking a Physical Design Engineer to translate RTL designs into optimized silicon implementations, covering floorplanning, placement, CTS, routing, and sign-off for high-performance VR/AR chips. You will collaborate with architecture, design, and verification teams to define physical implementation strategies for wearable devices.

The role requires 6+ years in physical design, expertise in timing closure, power integrity, and advanced node flows.